Device and circuit design challenges in the digital subthreshold region for ultralow-power applications

VLSI Design

Volumn 2009, Issue , 2009, Pages

  Vaddi, Ramesh ^a   Dasgupta, S ^a   Agarwal, R P ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY ROORKEE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 65649122269     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/2009/283702     Document Type: Review

References (55)

1. Chandrakasan A. P., Sheng S., Brodersen R. W., Low-power CMOS digital design IEEE Journal of Solid-State Circuits 1992 27 4 473 484
2. Paul B. C., Soeleman H., Roy K., An 8×8 subthreshold digital CMOS carry save array multiplier Proceedings of the 27th European Solid-State Circuits Conference (ESSCIRC'01) September 2001 Villach, Austria 377 380
3. Kim C. H.-I., Soeleman H., Roy K., Ultra-low-power DLMS adaptive filter for hearing aid applications IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2003 11 6 1058 1067
4. Wang A., Chandrakasan A. P., A 180mV FFT processor using subthreshold circuit techniques 1 Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC'04) February 2004 San Francisco, Calif, USA 292 529
5. Wang A., Chandrakasan A. P., A 180-mV subthreshold FFT processor using a minimum energy design methodology IEEE Journal of Solid-State Circuits 2005 40 1 310 319
6. Zhai B., Nazhandali L., Olson J., A 2.60pJ/inst subthreshold sensor processor for optimal energy efficiency Proceedings of the IEEE Symposium on VLSI Circuits (VLSIC'06) June 2006 Honolulu, Hawaii, USA 154 155
7. Calhoun B. H., Wang A., Verma N., Chandrakasan A. P., Subthreshold design: the challenges of minimizing circuit energy Proceedings of the 11th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'06) October 2006 Tegernsee, Germany 366 368
8. Taur Y., Ning T. H., Fundamentals of Modern VLSI Devices 1998 Cambridge, UK Cambridge University Press
9. Paul B. C., Raychowdhury A., Roy K., Device optimization for digital subthreshold logic operation IEEE Transactions on Electron Devices 2005 52 2 237 247
10. Keane J., Eom H., Kim T.-H., Sapatnekar S., Kim C., Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing Proceedings of the 43rd Annual Conference on Design Automation (DAC'06) July 2006 San Francisco, Calif, USA 425 428
11. Kim T.-H., Keane J., Eom H., Kim C. H., Utilizing reverse short-channel effect for optimal subthreshold circuit design IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2007 15 7 821 829
12. Paul B. C., Roy K., Oxide thickness optimization for digital subthreshold operation IEEE Transactions on Electron Devices 2008 55 2 685 688
13. Kim J.-J., Roy K., Double gate-MOSFET subthreshold circuit for ultralow power applications IEEE Transactions on Electron Devices 2004 51 9 1468 1474
14. Paul B. C., Bansal A., Roy K., Underlap DGMOS for digital-subthreshold operation IEEE Transactions on Electron Devices 2006 53 4 910 913
15. Roy K., Mahmoodi H., Mukhopadhyay S., Ananthan H., Bansal A., Cakici T., Double-gate SOI devices for low-power and high-performance applications Proceedings of the 19th International Conference on VLSI Design. Held jointly with 5th International Conference on Embedded Systems Design January 2006 Hyderabad, India 445 452
16. Raychowdhury A., Paul B. C., Bhunia S., Roy K., Ultralow power computing with subthreshold leakage: a comparative study of bulk and SOI technologies 1 Proceedings of the Conference on Design, Automation and Test in Europe (DATE'06) 2006 Munich, Germany 856 861
17. Raychowdhury A., Paul B. C., Bhunia S., Roy K., Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2005 13 11 1213 1224
18. Soeleman H., Roy K., Ultra-low power digital subthreshold logic circuits Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'99) August 1999 San Diego, Calif, USA 94 96
19. Soeleman H., Roy K., Digital CMOS logic operation in the subthreshold region Proceedings of the 10th IEEE Great Lakes Symposium on VLSI (GLSVLSI'00) March 2000 Chicago, Ill, USA 107 112
20. Soeleman H., Roy K., Paul B. C., Robust subthreshold logic for ultra-low power operation IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2001 9 1 90 99
21. Soeleman H., Roy K., Paul B. C., Robust ultra-low power subthreshold DTMOS logic Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'00) July 2000 Rapallo, Italy 25 30
22. Soeleman H., Roy K., Paul B. C., Sub-domino logic: ultra-low power dynamic subthreshold digital logic Proceedings of the 14th International Conference on VLSI Design (VLSI DESIGN'01) January 2001 Bangalore, India 211 214
23. Akgun O. C., Leblebici Y., Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'06) May 2006 Island of Kos, Greece 1251 1254
24. Moalemi V., Afzali-Kusha A., Subthreshold pass transistor logic for ultra-low power operation Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07) March 2007 Porto Alegre, Brazil 490 491
25. Melek L. A. P., Schneider M. C., Galup-Montoro C., Body-bias compensation technique for subthreshold CMOS static loqic gates Proceedings of the 17th Symposium on Integrated Cicuits and Systems Design (SBCCI'04) September 2004 Pernambuco, Brazil 267 272
26. Jayakumar N., Khatri S. P., A variation-tolerant subthreshold design approach Proceedings of the 42nd Design Automation Conference (DAC'05) June 2005 Anaheim, Calif, USA 716 719
27. Zhai B., Hanson S., Blaauw D., Sylvester D., Analysis and mitigation of variability in subthreshold design Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'05) August 2005 San Diego, Calif, USA 20 25
28. Kwong J., Chandrakasan A. P., Variation-driven device sizing for minimum energy subthreshold circuits Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'06) October 2006 Tegernsee, Germany 8 13
29. De Vita G., Iannaccone G., A voltage regulator for subthreshold logic with low sensitivity to temperature and process variations Proceedings of the 54th IEEE International Solid-State Circuits Conference (ISSCC'07) February 2007 San Francisco, Calif, USA 530 620
30. Verma N., Kwong J., Chandrakasan A. P., Nanometer MOSFET variation in minimum energy subthreshold circuits IEEE Transactions on Electron Devices 2008 55 1 163 174
31. Calhoun B. H., Wang A., Chandrakasan A. P., Device sizing for minimum energy operation in subthreshold circuits Proceedings of the IEEE Custom Integrated Circuits Conference (CICC'04) October 2004 San Jose, Calif, USA 95 98
32. Calhoun B. H., Wang A., Chandrakasan A. P., Modeling and sizing for minimum energy operation in subthreshold circuits IEEE Journal of Solid-State Circuits 2005 40 9 1778 1786
33. Seok M., Hanson S., Sylvester D., Blaauw D., Analysis and optimization of sleep modes in subthreshold circuit design Proceedings of the 44th Annual Conference on Design Automation (DAC'07) June 2007 San Diego, Calif, USA 694 699
34. Ramadass Y. K., Chandrakasan A. P., Minimum energy tracking loop with embedded DC-DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS IEEE Journal of Solid-State Circuits 2008 43 1 256 265
35. Wang A., Chandrakasan A. P., Kosonocky S. V., Optimal supply and threshold scaling for subthreshold CMOS circuits Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02) April 2002 Pittsburgh, Pa, USA 5 9
36. Calhoun B. H., Chandrakasan A. P., Ultra-dynamic voltage scaling (UDVS) using subthreshold operation and local voltage dithering IEEE Journal of Solid-State Circuits 2006 41 1 238 245
37. Hanson S., Seok M., Sylvester D., Blaauw D., Nanometer device scaling in subthreshold circuits Proceedings of the 44th Design Automation Conference (DAC'07) June 2007 San Diego, Calif, USA 700 705
38. Hanson S., Seok M., Sylvester D., Blaauw D., Nanometer device scaling in subthreshold logic and SRAM IEEE Transactions on Electron Devices 2008 55 1 175 185
39. Calhoun B. H., Chandrakasan A. P., A 256kb subthreshold SRAM in 65nm CMOS Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC'06) February 2006 San Francisco, Calif, USA 2592 2601
40. Chen J., Clark L. T., Chen T.-H., An ultra-low-power memory with a subthreshold power supply voltage IEEE Journal of Solid-State Circuits 2006 41 10 2344 2353
41. Chavan A., Dukle G., Graniello B., MacDonald E., Robust ultra-low power subthreshold logic flip-flop design for reconfigurable architectures Proceedings of the IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig'06) September 2006 San Luis Potosi, Mexico 1 7
42. Calhoun B. H., Chandrakasan A. P., A 256-kb 65-nm subthreshold SRAM design for ultra-low-voltage operation IEEE Journal of Solid-State Circuits 2007 42 3 680 688
43. Kulkarni J. P., Kim K., Roy K., A 160 mV robust schmitt trigger based subthreshold SRAM IEEE Journal of Solid-State Circuits 2007 42 10 2303 2313
44. Ramirez R. J., Variability-aware design of subthreshold devices, M.S. thesis 2007 Waterloo, Canada Electrical and Computer Engineering Department, University of Waterloo
45. Calhoun B. H., Low energy digital circuit design using subthreshold operation, Ph.D. thesis December 2005 Cambridge, Mass, USA Electrical and Computer Engineering Department, MIT
46. Wang A., An ultra low voltage FFT processor using energy aware techniques, Ph.D. thesis February 2004 Cambridge, Mass, USA Electrical and Computer Engineering Department, MIT
47. Wind S. J., Appenzeller J., Martel R., Derycke V., Avouris Ph., Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes Applied Physics Letters 2002 80 20 3817 3819
48. Javey A., Kim H., Brink M., High-k dielectrics for advanced carbon-nanotube transistors and logic gates Nature Materials 2002 1 4 241 246
49. Lundstrom M., Ren Z., Essential physics of carrier transport in nanoscale MOSFETs IEEE Transactions on Electron Devices 2002 49 1 133 141
50. Guo J., Datta S., Lundstrom M., Assessment of silicon MOS and carbon nanotube FET performance limits using a general theory of ballistic transistors Proceedings of the IEEE International Electron Devices Meeting (IEDM'02) December 2002 San Francisco, Calif, USA 711 714
51. Martel R., Wong H.-S. P., Chan K., Avouris P., Carbon nanotube field effect transistors for logic applications Proceedings of the International Electron Devices Meeting (IEDM'01) December 2001 Washington, DC, USA 7.5.1 7.5.4
52. Collier N., Jean R., Kala S., Ndai P., Application of CNFETs and MOSFETs circuits at subthreshold. Circuits Team SURI Program, 2003
53. Deng J., Wong H.-S. P., A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-part II: full device model and circuit performance benchmarking IEEE Transactions on Electron Devices 2007 54 12 3195 3205
54. Guo J., Lundstrom M., Role of phonon scattering in carbon nanotube field-effect transistors Applied Physics Letters 2005 86 19 3
55. Deng J., Wong H.-S. P., Modeling and analysis of planar-gate electrostatic capacitance of 1-D FET with multiple cylindrical conducting channels IEEE Transactions on Electron Devices 2007 54 9 2377 2385