Body-bias compensation technique for subthreshold CMOS static loqic gates

Proceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004

Volumn , Issue , 2004, Pages 267-272

  Melek, Luiz Alberto P ^a   Schneider, Márcio C ^a   Galup Montoro, Carlos ^a  

^a FEDERAL UNIVERSITY OF SANTA CATARINA   (Brazil)

Author keywords

Body bias compensation; CMOS; Logic circuits; Low power; Static logic; Subthreshold

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DECODING; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; ERROR COMPENSATION; FIR FILTERS; MATHEMATICAL MODELS; TRANSISTORS;

BODY-BIAS COMPENSATION; LOW-POWER; STATIC LOGIC; SUBTHRESHOLD;

LOGIC GATES;

EID: 14244249218     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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