Underlap DGMOS for digital-subthreshold operation

IEEE Transactions on Electron Devices

Volumn 53, Issue 4, 2006, Pages 910-913

  Paul, Bipul C ^a   Bansal, Aditya ^b   Roy, Kaushik ^b  

^a Toshiba America Research Inc   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Subthreshold operation; Ultralow power operation; Underlap double gate MOS (DGMOS)

Indexed keywords

ADDERS; DIGITAL CIRCUITS; GATES (TRANSISTOR); OPTIMIZATION; PERFORMANCE; POWER ELECTRONICS; SEMICONDUCTOR DEVICE STRUCTURES;

DIGITAL SUBTHRESHOLD OPERATION; FULL-ADDER CIRCUIT; POWER DISSIPATION;

MOSFET DEVICES;

EID: 33645748445     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.870271     Document Type: Article

References (10)

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