Robust ultra-low power subthreshold logic flip-flop design for reconfigurable architectures

Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006

Volumn , Issue , 2006, Pages 142-148

  Chavan, Ameet ^a   Dukle, Gaurav ^a   Graniello, Ben ^b   Macdonald, Eric ^a  

^a 500 W University Avenue   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSERVATION; EFFICIENCY; ELECTRIC POWER UTILIZATION; ERRORS; FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLIP FLOP CIRCUITS; FUZZY LOGIC; HARDNESS; QUALITY ASSURANCE; RADIATION; RADIATION EFFECTS; RELIABILITY; SULFATE MINERALS;

(OTDR) TECHNOLOGY; BATTERY-POWERED APPLICATIONS; FLIP-FLOP DESIGNS; FUNCTIONAL OPERATIONS; HIGH-RELIABILITY; INTERNATIONAL CONFERENCES; LOW-POWER CONSUMPTION; LOW-VOLTAGE (LV); MINIMUM ENERGY; NOISE IMMUNITY; PERFORMANCE DEGRADATION; RADIATION HARDNESS; RE CONFIGURABILITY; RE CONFIGURABLE ARCHITECTURE; RE CONFIGURABLE COMPUTING (RCC); RE-CONFIGURABLE; REDUCED POWER CONSUMPTION; SPACE ELECTRONICS; SUB THRESHOLDS; SUBTHRESHOLD LOGIC; ULTRA LOW POWER (ULP);

ENERGY EFFICIENCY;

EID: 46449104682     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RECONF.2006.307764     Document Type: Conference Paper

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