Device optimization for digital subthreshold logic operation

IEEE Transactions on Electron Devices

Volumn 52, Issue 2, 2005, Pages 237-247

  Paul, Bipul C ^a   Raychowdhury, Arijit ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Device optimization; Subthreshold operation; Ultralow power applications

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; LOGIC CIRCUITS; LOGIC DESIGN; MATHEMATICAL MODELS; OPTIMIZATION; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE; TRANSISTORS;

DEVICE OPTIMIZATION; POWER DELAY PRODUCT; SUBTHRESHOLD OPERATION; ULTRALOW POWER APPLICATION;

DIGITAL CIRCUITS;

EID: 13344280331     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.842538     Document Type: Article

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