Sub-threshold design: The challenges of minimizing circuit energy

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 366-368

  Calhoun, B H ^a   Wang, A ^b   Verma, N ^c   Chandrakasan, A ^c  

^a UNIVERSITY OF VIRGINIA   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Dynamic voltage scaling; Low voltage memory; Process variations; Sub threshold digital circuits; Sub threshold logic

Indexed keywords

DYNAMIC VOLTAGE SCALING; LOW VOLTAGE MEMORY; PROCESS VARIATIONS; SUB-THRESHOLD DIGITAL CIRCUITS; SUB-THRESHOLD LOGIC;

DIGITAL CIRCUITS; ENERGY UTILIZATION; MICROPROCESSOR CHIPS;

ELECTRIC NETWORK ANALYSIS;

EID: 34247225479     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165661     Document Type: Conference Paper

References (14)

1. Swanson and Meindl, JSSC, 1972.
2. Vittoz and Fellrath, JSSC, 1977.
3. Mead, Addison-Wesley, 1989.
4. Soeleman and Roy, ISLPED, 1999.
5. Paul, Soeleman, and Roy, ESSCIRC, 2001.
6. Deen, Kazemeini, and Naseh, ICCDCS, 2002.
7. Wang, Chandrakasan, and Kosonocky, SVLSI, 2002.
8. Zhai, Blaauw, Sylvester, and Flautner, DAC, 2004.
9. Calhoun and Chandrakasan, ISLPED, 2004.
10. Sze, Blazquez, Bhardwaj, and Chandrakasan, ICASSP, 2006.
11. Wang and Chandrakasan, ISSCC, 2004.
12. Calhoun and Chandrakasan, ISSCC, 2005.
13. Seevinck, List, and Lohstroh, JSSC, 1987.
14. Calhoun and Chandrakasan, ISSCC, 2006.