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Volumn , Issue , 2005, Pages 716-719

A Variation-tolerant sub-threshold design approach

Author keywords

Body biasing; Self adjusting; Sub threshold; Variation tolerant

Indexed keywords

DETECTORS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; POWER CONTROL;

EID: 27944462775     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193905     Document Type: Conference Paper
Times cited : (24)

References (11)
  • 2
    • 0033688320 scopus 로고    scopus 로고
    • Digital CMOS logic operation in the sub-threshold region
    • Mar
    • H. Soeleman and K. Roy, "Digital CMOS logic operation in the sub-threshold region," in Tenth Great Lakes Symposium on VLSI, pp. 107-112, Mar 2000.
    • (2000) Tenth Great Lakes Symposium on VLSI , pp. 107-112
    • Soeleman, H.1    Roy, K.2
  • 5
    • 0036858210 scopus 로고    scopus 로고
    • Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage, in
    • Nov
    • J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," in IEEE Journal of Solid-State Circuits, vol. 37, pp. 1396-1402, Nov 2002.
    • (2002) IEEE Journal of Solid-state Circuits , vol.37 , pp. 1396-1402
    • Tschanz, J.1    Kao, J.2    Narendra, S.3    Nair, R.4    Antoniadis, D.5    Chandrakasan, A.6    De, V.7
  • 7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.