Weak inversion performance of CMOS and DCVSPG logic families in sub-300mV range

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 1251-1254

  Akgun, Omer Can ^a   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; FORMAL LOGIC; LOGIC GATES; STANDARDS;

DIFFERENTIAL CASCODE VOLTAGE SWITCH PASS GATE (DCVSPG) LOGIC; ENERGY-DELAY-PRODUCT (EDP); SUBTHRESHOLD OPERATIONS;

CMOS INTEGRATED CIRCUITS;

EID: 34547296568     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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