Subthreshold pass transistor logic for ultra-low power operation

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Volumn , Issue , 2007, Pages 490-491

  Moalemi, Vahid ^a   Afzali Kusha, Ali ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POWER SYSTEMS; SENSITIVITY ANALYSIS; TRANSISTORS;

DYNAMIC THRESHOLD PASSTRANSISTOR LOGIC (SUB-DTPT); PASSTRANSISTOR XOR STRUCTURES; SUBTHRESHOLD PASSTRANSISTOR LOGIC (SUB-PT); ULTRA-LOW POWER OPERATION;

LOGIC CIRCUITS;

EID: 36348929267     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2007.94     Document Type: Conference Paper

References (5)

1. H. Soeleman, K. Roy, and B. C. Paul, "Robust Ultra-Low Power Sub-threshold DTMOS Logic", in Int. Symp. Low Power Electron. Design, 2000.
2. B. H. Calhoun and A. Chandrakasan, "Characterizing and modeling minimum energy operation for subthreshold circuits," in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), 2004, pp. 90-95.
3. B. H. Calhoun, A. Wang and A. Chandrakasan, "Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits", IEEE Journal Of Solid-State Circuits, vol. 40, NO. 9, September 2005.
4. H. Soeleman, K. Roy, and B. C. Paul, "Robust Subthreshold Logic for Ultra-Low Power Operation," IEEE Trans. VLSI Syst., vol. 9, pp. 90-99,Feb. 2001.
5. Hung Tien Bui, Yuke Wang, and Yingtao Jiang, "Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR-XNOR Gates," IEEE Trans. on circuits and systems - II: analog and digital signal processing, vol. 49, no. 1, January 2002 pp, 25-30.