Device sizing for minimum energy operation in subthreshold circuits

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 95-98

  Calhoun, Benton H ^a   Wang, Alice ^a   Chandrakasan, Anantha ^a  

^a Department of Electrical Engineering and Computer Science   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY CIRCUITS; ENERGY CONSTRAINTS; SUPPLY VOLTAGE;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ENERGY UTILIZATION; FIR FILTERS; MICROPROCESSOR CHIPS;

DIGITAL CIRCUITS;

EID: 17044396646     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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2. J. Burr and A. Peterson, "Ultra Low Power CMOS Technology," 3rd NASA Symposium on VLSI Design, pp. 4.2.1-4.2.13, 1991.
3. A. Wang and A. Chandrakasan, "A 180mV FFT Processor Using Subthreshold Circuit Techniques," Intl. Solid-State Circuits Conference, 2004.
4. E. Vittoz, "Low-Power Design: Ways to Approach the Limits," Intl. Solid-State Circuits Conf., 1994.
5. B. H. Calhoun and A. Chandrakasan, "Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits," ISLPED, 2004.
6. G. Schrom and S. Selberherr, "Ultra-Low-Power CMOS Technologies," Intl. Semiconductor Conf., pp. 237 - 246, 1996
7. A. Bryant, et al., "Low-Power CMOS at Vdd=4kT/q," Device Research Conference, pp. 25-27, 2001.
8. Ono, Atsuki, et al., "TED Control Technology for Suppression of Reverse Narrow Channel Effect in 0.1 μm MOS Devices," IEDM, 1997.
9. C. Piguet, "Design of Low-Power Libraries," Intl. Conf. on Electronics, Circuits and Systems, vol. 2, pp. 175-180, Sept. 1998.
10. C. Piguet, et al., "Low-Power Low-Voltage Library Cells and Memories," pp. 1521-1524, 2001.