Impact of high-Κ gate stacks on transport and variability in nano-CMOS devices

Journal of Computational and Theoretical Nanoscience

Volumn 5, Issue 6, 2008, Pages 1072-1088

  Watling, J R ^a   Brown, A R ^a   Ferrari, G ^b   Barker, J R ^a   Bersuker, G ^c   Zeitzoff, P ^d   Asenov, A ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

^b UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^c SEMATECH   (United States)

^d FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

High ; Intrinsic fluctuations; Mobility; Monte carlo simulation

Indexed keywords

CARRIER MOBILITY; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; GATE DIELECTRICS; HIGH ELECTRON MOBILITY TRANSISTORS; INTELLIGENT SYSTEMS; LEAKAGE CURRENTS; LOGIC GATES; MONTE CARLO METHODS; NANOTECHNOLOGY; PHONON SCATTERING; PHONONS; SILICON;

90 NM TECHNOLOGY NODE; EFFECTIVE GATE LENGTH; ENSEMBLE MONTE CARLO DEVICE SIMULATORS; GATE-LEAKAGE CURRENT; INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS; INTRINSIC FLUCTUATIONS; MOBILITY DEGRADATION; SOFT-OPTICAL PHONONS;

MOSFET DEVICES;

EID: 48949087777     PISSN: 15461955     EISSN: None     Source Type: Journal    
DOI: 10.1166/jctn.2008.2542     Document Type: Review

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