Mobility evaluation in transistors with charge-trapping gate dielectrics

Applied Physics Letters

Volumn 87, Issue 4, 2005, Pages

  Bersuker, G ^a   Zeitzoff, P ^a   Sim, J H ^a   Lee, B H ^a   Choi, R ^a   Brown, G ^a   Young, C D ^a  

^a SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; ELECTRON TRAPPING; GATE DIELECTRICS; STRUCTURAL DEFECTS;

CARRIER MOBILITY; CRYSTAL DEFECTS; ELECTRIC POTENTIAL; ELECTRON TRAPS; GATES (TRANSISTOR); SEMICONDUCTOR GROWTH; SILICA; TRANSISTORS;

DIELECTRIC MATERIALS;

EID: 23744478184     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1995956     Document Type: Article

References (9)

1. MRS Bulletin, edited by, R. M. Wallace, and, G. Wilks, (2002).
2. G. Bersuker, P. Zeitzoff, G. Brown, and H. R. Huff, Mater. Today 26 (2004).
3. G. Bersuker, J. H. Sim, C. D. Young, R. Choi, B. H. Lee, P. Lysaght, G. A. Brown, P. M. Zeitzoff, M. Gardner, R. W. Murto, and H. R. Huff, Proceedings of MRS Spring Meeting, 2004 (to be published).
4. W. Zhu, J.-P. Han, and T. P. Ma, IEEE Trans. Electron Devices 51, 98 (2004).
5. A. Kerber, E. Cartier, L. A. Ragnarsson, M. Rosmeulen, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, and G. Groeseneken, VLSI Technology Symposium Digest, Kyoto, 2003, p. 159.
6. See reviews in IEEE Trans. Device Mater. Reliab. (2005).
7. C. D. Young, G. Bersuker, G. A. Brown, P. Lysaght, P. Zeitzoff, R. W. Murto, and H. R. Huff, IEEE-IRPS Proceeding, 2004, p. 597.
8. J. H. Sim, B. H. Lee, R. Choi, K. Matthews, D. L. Kwong, P. Tsui, and G. Bersuker, DRC 99 (2004).
9. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, IEEE Electron Device Lett. 25, 408 (2004).