High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

IEEE Transactions on Electron Devices

Volumn 49, Issue 12, 2002, Pages 2263-2270

  Inaba, Satoshi ^a   Okano, Kimitoshi ^a   Matsuda, Satoshi ^a   Fujiwara, Makoto ^a   Hokazono, Akira ^a   Adachi, Kanna ^a   Ohuchi, Kazuya ^a   Suto, Hiroyuki ^a   Fukui, Hironobu ^a   Shimizu, Takashi ^a   Mori, Shinji ^a   Oguma, Hideki ^a   Murakoshi, Atsushi ^a   Itani, Takaharu ^a   Iinuma, Toshihiko ^a   Kudo, Tomoyasu ^a   Shibata, Hidenori ^a,c   Taniguchi, Shuichi ^a   Takayanagi, Mariko ^a   Azuma, Atsushi ^a,b   Oyamatsu, Hisato ^a   Suguro, Kyoichi ^a   Katsumata, Yasuhiro ^a   Toyoshima, Yoshiaki ^a,b   Ishiuchi, Hidemi ^a   more..

^a TOSHIBA CORPORATION   (Japan)

^b IBM   (United States)

^c Process and Manufacturing Engineering Center   (Japan)

Author keywords

Boron penetration; CMOS; Current drive; Gate depletion; Gmmax; MOSFET; Nickel; NO oxynitride; Salicide; Silicon; Sub 50 nm; Thermal budget

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC CURRENTS; GATES (TRANSISTOR); NICKEL COMPOUNDS; NITRIDES; POLYSILICON; SEMICONDUCTING BORON; SEMICONDUCTOR JUNCTIONS; THERMAL EFFECTS;

BORON PENETRATION; GATE DEPLETION; GATE LENGTH CMOS; NICKEL SALICIDE; OXYNITRIDE; THERMAL BUDGET;

CMOS INTEGRATED CIRCUITS;

EID: 0037004304     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.805575     Document Type: Article

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