On variable clock methods for path delay testing of sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 11, 1997, Pages 1237-1249

  Chakraborty, Tapan J ^a,b   Agrawal, Vishwani D ^a,b   Bushnell, Michael L ^a,b  

^a LUCENT TECHNOLOGIES   (United States)

^b RUTGERS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL CIRCUITS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; TESTING;

SEQUENTIAL CIRCUITS; VARIABLE CLOCK METHODS;

INTEGRATED CIRCUITS;

EID: 0031274402     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.663815     Document Type: Article

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