Classification and identification of nonrobust untestable path delay faults

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 8, 1996, Pages 845-853

  Cheng, Kwang Ting ^a   Chen, Hsi Chuan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; ERROR DETECTION; FAILURE ANALYSIS; HEURISTIC METHODS; IDENTIFICATION (CONTROL SYSTEMS); LOGIC GATES; REDUNDANCY;

BENCHMARK CIRCUITS; FUNCTIONAL REDUNDANCY; PATH DELAY FAULTS; PATH SELECTION;

DELAY CIRCUITS;

EID: 0030214852     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.511566     Document Type: Article

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