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Volumn , Issue , 1992, Pages 365-374
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Design for testability: Using scanpath techniques for path-delay test and measurement
a
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Author keywords
[No Author keywords available]
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Indexed keywords
AUTOMATIC TESTING;
FLIP FLOP CIRCUITS;
LOGIC CIRCUITS;
INPUT/OUTPUT DELAYS;
PATH DELAY DEPTHS;
SCAN PATH TECHNIQUES;
ELECTRON DEVICE TESTING;
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EID: 0026676975
PISSN: 07431686
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (112)
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References (7)
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