Modeling and Testing for Timing Faults in Synchronous Sequential Circuits Studying failures in the combinational logic and storage elements of synchronous sequential circuits may help detect physical faults that cause timing problems

IEEE Design and Test of Computers

Volumn 1, Issue 4, 1984, Pages 62-74

  Malaiya, Yashwant K ^a   Narayanaswamy, Ramesh ^a  

^a Veterinary Dentistry and Oral Surgery   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY FAULT; EDGE-TRIGGERED FLIPFLOPS; SCAN DESIGN TESTING; TIGHT DESIGN; TIMING FAULT MODEL;

DATA STORAGE, SEMICONDUCTOR - TESTING; INTEGRATED CIRCUITS, VLSI - TESTING; LOGIC CIRCUITS, COMBINATORIAL;

LOGIC CIRCUITS, SEQUENTIAL;

EID: 0021521388     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.1984.5005692     Document Type: Article

References (36)

1. M.A. Breuer, “The Effects of Races, Delays and Delay Faults on Test Generation,” IEEE Trans. Computers, Oct. 1974, pp. 1078–1092.
2. E.P. Hsieh et al., “Delay Test Generation,” Proc. 14th Design Automation Conf, June 1977, pp. 486–491.
3. C. Timoc et al., “Logical Model for Physical Failures,” Proc. Int'l Test Conf., Oct. 1983, pp. 546–553.
4. P. Banerjee and J.A. Abraham, “Generating Tests for Physical Failures in MOS Logic Circuits,” Proc. Int'l Test Conf., Oct. 1983, pp. 554–559.
5. D.M. Wu and C.E. Radke, “The Effects of Random Defects and Tester Accuracy on the Quality and Yield of VLSI Circuits,” Proc. 14th Int'l Conf. Fault-Tolerant Computing, June 1984, pp. 56–63.
6. R.B. Hitchcock, G.L. Smith and D.D. Cheng, “Timing Analysis of Computer Hardware,” IBM J. Research and Development, Vol. 26, No. 1, Jan. 1982, pp. 100–105.
7. C. Seitz, “System Timing,” Introduction to VLSI Systems by C. Mead and L. Conway, Addison-Wesley, 1980, ch 7.
8. J.A. Marques and A. Cunha, “Clocking of VLSI Circuits,” in VLSI Architectures, ed. B. Randall and P.C. Treleven, Prentice-Hall International, 1983.
9. M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design of Digital Systems, Computer Science Press, 1976.
10. T.M. Storey and J.W. Berry, “Delay Test Simulation,” Proc. 14th Design Automation Conf., June 1977, pp. 492–494.
11. J.D. Lesser and J.J. Shedletsky, “An Experimental Delay Test Generator for LSI Logic,” IEEE Trans. Computers, Mar. 1980, pp. 235–248.
12. C.C. Liaw, S.Y.H. Su, and Y.K. Malaiya, “Test Generation for Delay Faults Using Stuck-At-Fault Test Set,” Proc. 1980 Int'l Test Conf, Nov. 1980, pp. 167–175.
13. K. Son and D.K. Pradhan, “Testing for Delay Faults in a PLA,” Proc. Int'l Conf. Circuits and Computers, Sept. 1982, pp. 346–349.
14. T. Hayashi, “A Delay Test Generator for Logic LSI,” Proc. 14th Int'l Conf. Fault-Tolerant Computing, June 1984, pp. 146–149.
15. Y.K. Malaiya and R. Narayanaswamy, “Testing for Timing Faults in Synchronous Sequential Integrated Circuits,” Proc. 1983 Int'l Test Conf., Oct. 1983, pp. 560–571.
16. R.B. Hitchcock, Sr., “Timing Verification and the Timing Analysis Program,” Proc. 19th Design Automation Conf., June 1982, pp. 594–604.
17. K. Okazaki, T. Moriya, and T. Yahara, “A Multiple Media Delay Simulator for MOS LSI Circuits,” Proc. 20th Design Automation Conf., June 1983, pp. 279–285.
18. V.D. Agrawal, “Synchronous Path Analysis in MOS Circuit Simulator,” Proc. 19th Design Automation Conf, June 1982, pp. 629–635.
19. E.J. McCluskey, Logic Design, chapter 7, 1984, to be published.
20. B.K. Fawcett, Maximal Clocking Rates for Pipelined Digital Systems, MS thesis, University of Illinois at Urbana, 1976.
21. M.S. Zemgalis and W.H. Debany, Jr., “Making Accurate AC Measurements on Automatic Test Equipment,” Proc. Autotestcon, 1982, pp. 504–508.
22. S.M. Unger and C.J. Tan, “Optimal Clocking Schemes for High Speed Digital Systems.” Proc. ICCD, 1983, pp. 366–369.
23. T.J. Chaney and C.E. Molnar, “Anomalous Behaviour of Synchronizer and Arbiter Circuits,” IEEE Trans. Computers, Apr. 1973, pp. 421–422.
24. J.F. Wakerly, “The Intel MCS-48 Microcomputer Family: A Critique,” Computer, Feb. 1979, pp. 22–31.
25. E.H. Frank and R.F. Sproull, “Two Timing Samplers,” Proc. Caltech Conf. VLSI, Jan. 1981, pp. 127–134.
26. J. Newkirk and R. Mathews, The VLSI Designers Library, Addison-Wesley, 1983, ch. 3.
27. Bipolar Microprocessor Logic and Interface, American Micro Devices, 1983, pp. 8.4–8.7.
28. P.A. Stoll, “How to Avoid Synchronization Problems,” VLSI Design, Nov./Dec. 1982, pp. 56–59.
29. C.H. Chen, Designing Testable Synchronous Logic,” Proc. 1981 Int'l Test Conf, Oct. 1981, pp. 89–94.
30. C.H. Chen, “Design Methodology for Testable VLSI,” Proc. Compcon, 1981, pp. 168–173.
31. John B. Peatman, Digital Hardware Design, McGraw-Hill, 1980, pp. 246–306.
32. L.C. Bening, T.A. Lane, and C.R. Alexander, “-Developments in Logic Network Path Delay Analysis,” Proc. 19th Design Automation Conf, June 1982, pp. 605–615.
33. E.B. Eichelberger and T.W. Williams, “A Logic Design Structure for LSI Testability,” J. Design Automation and Fault Tolerant Computing, May 1978, pp. 165–178.
34. S. DasGupta, R.G. Walther, and T.W. Williams, “An Enhancement to LSSD in Reliability, Availability and Serviceability, Proc. 11th Int'l Symp. Fault-Tolerant Computing, June 1981, pp. 32–34.
35. Capable Test Systems, Application Note 107, Computer Automation Industrial Products Div., 1979, p. 5.
36. Z. Barzilai and B.K. Rosen, “Comparison of AC Self-Testing Procedures,” Proc. 1983 Int'l Test Conf, Oct. 1983, pp. 89–94.