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Volumn , Issue , 1995, Pages 132-138

Test vector generation for parametric path delay faults

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ELECTRIC FAULT CURRENTS; FABRICATION; LOGIC DESIGN; LOGIC GATES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SIGNAL PROCESSING; TIMING CIRCUITS; VECTORS;

EID: 0029510940     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (18)
  • Reference 정보가 존재하지 않습니다.

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.