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Volumn , Issue , 1995, Pages 132-138
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Test vector generation for parametric path delay faults
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Author keywords
[No Author keywords available]
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Indexed keywords
DELAY CIRCUITS;
ELECTRIC FAULT CURRENTS;
FABRICATION;
LOGIC DESIGN;
LOGIC GATES;
MATHEMATICAL MODELS;
MICROPROCESSOR CHIPS;
SIGNAL PROCESSING;
TIMING CIRCUITS;
VECTORS;
BENCHMARK CIRCUITS;
PATH DELAY FAULTS;
SENSITIZATION APPROACH;
TEST VECTOR GENERATION;
INTEGRATED CIRCUIT TESTING;
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EID: 0029510940
PISSN: 10893539
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (8)
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References (18)
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