Combinational profiles of sequential benchmark circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1989, Pages 1929-1934

  Brglez, Franc ^a   Bryan, David ^a   Kozminski, Krzysztof ^a  

^a MCNC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, FLIP FLOP; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS, COMBINATORIAL--TESTING;

DIGITAL SEQUENTIAL CIRCUITS; GATE LEVEL; SCAN BASED SYSTEMS; SEQUENTIAL BENCHMARK CIRCUITS; TEST GENERATION;

AUTOMATIC TESTING;

EID: 0024913805     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)