Test generation system for path delay faults

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1989, Pages 40-43

  Patil, Srinivas ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER METATHEORY--MANY VALUED LOGICS; LOGIC DESIGN;

5-VALUED LOGIC; COMBINATIONAL BENCHMARK CIRCUITS; PATH DELAY FAULTS; TEST GENERATION; TEST PATTERN GENERATOR;

INTEGRATED CIRCUIT TESTING;

EID: 0024946210     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)