Path Delay Fault Simulation of Sequential Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 1, Issue 4, 1993, Pages 453-461

  Bose, Soumitra ^a   Agrawal, Prathima ^a   Agrawal, Vishwani D ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC FAULT LOCATION; ERROR ANALYSIS; FLIP FLOP CIRCUITS; HAZARDS AND RACE CONDITIONS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; STATE ASSIGNMENT; VECTORS;

COMBINATIONAL ROBUSTNESS; ISCAS '89 SEQUENTIAL BENCHMARKS; PATH DELAY FAULT SIMULATION;

SEQUENTIAL CIRCUITS;

EID: 0027812826     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.250193     Document Type: Article

References (11)

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