On the fault coverage of gate delay fault detecting tests

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 1, 1997, Pages 78-94

  Pramanick, Ankan K ^a   Reddy, Sudhakar M ^a  

^a Rio Design Automation Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; COMPUTER SIMULATION; ERROR DETECTION; FAILURE ANALYSIS; MATHEMATICAL MODELS; TESTING;

CLOCK INTERVAL; CLOCK PERIOD; GATE DELAY FAULT DETECTING TEST;

LOGIC CIRCUITS;

EID: 0030649915     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.559333     Document Type: Article

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