Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 11, Issue 1, 1997, Pages 55-67

  Gharaybeh, Marwan A ^a,b,c,d   Bushnell, Michael L ^b,e,f   Agrawal, Vishwani D ^{c,g,h,i,j,k,l,m}  

^a SYNOPSYS INC   (United States)

^b RUTGERS UNIVERSITY   (United States)

^c LUCENT TECHNOLOGIES   (United States)

^d UNIVERSITY OF JORDAN   (Jordan)

^e CARNEGIE MELLON UNIVERSITY   (United States)

^f NATIONAL SCIENCE FOUNDATION   (United States)

^g INDIAN INSTITUTE OF TECHNOLOGY ROORKEE   (India)

^h UNIVERSITY OF ALLAHABAD   (India)

ⁱ INDIAN INSTITUTE OF SCIENCE   (India)

^j UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^k RUTGERS UNIVERSITY   (United States)

^l IEEE   (India)

^m ACM   (India)

more..

Author keywords

Delay test; Digital circuit testing; Fault models; Path delay faults; Test generation

Indexed keywords

COMBINATORIAL CIRCUITS; DIGITAL CIRCUITS; ELECTRIC NETWORK SYNTHESIS; VLSI CIRCUITS;

DELAY TESTING; PATH DELAY FAULTS; SINGLE STUCK AT FAULT TEST;

INTEGRATED CIRCUIT TESTING;

EID: 0031210023     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008247801050     Document Type: Article

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