Test Generation for Path Delay Faults Using Binary Decision Diagrams

IEEE Transactions on Computers

Volumn 44, Issue 3, 1995, Pages 434-447

  Bhattacharya, Debashis ^a   Agrawal, Prathima ^b   Agrawal, Vishwani D ^b  

^a YALE UNIVERSITY   (United States)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; CONSTRAINT THEORY; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; FUNCTIONS;

BINARY DECISION DIAGRAMS; BOOLEAN ALGEBRAIC TEST GENERATION; DELAY FAULT SCAN TESTING; DELAY FAULTS; REDUCED ORDERED BINARY DECISION DIAGRAMS; REDUNDANT DELAY FAULTS; ROBUST DELAY TESTS;

SEQUENTIAL CIRCUITS;

EID: 0029271036     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.372035     Document Type: Article

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