Delay test generation for synchronous sequential circuits

Volumn , Issue , 1989, Pages 144-152

  Devadas, Srinivas ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATA THEORY--SEQUENTIAL MACHINES; COMPUTER PROGRAMMING--ALGORITHMS; ELECTRONIC EQUIPMENT TESTING;

DELAY FAULTS; SEQUENTIAL DELAY REDUNDANCIES; STATE ASSIGNMENT ALGORITHM; SYNCHRONOUS SEQUENTIAL CIRCUITS; TEST GENERATION; TEST SEQUENCES;

LOGIC CIRCUITS, SEQUENTIAL;

EID: 0024915805     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)