On Computing the Sizes of Detected Delay Faults

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 3, 1990, Pages 299-312

  Iyengar, Vijay S ^a   Rosen, Barry K ^a   Waicukauski, John A ^b  

^a IBM RESEARCH   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE--DEFECTS; INTEGRATED CIRCUIT TESTING--COMPUTER AIDED ANALYSIS; LOGIC DEVICES--GATES;

DELAY FAULT TEST; FAULT SIMULATION; TEST GENERATION;

INTEGRATED CIRCUITS;

EID: 0025400935     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.46805     Document Type: Article

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