Synchronous path analysis in MOS circuit simulator

Proceedings - Design Automation Conference

Volumn , Issue , 1982, Pages 629-635

  Agrawal, Vishwani D ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; COMPUTER AIDED DESIGN; ELECTRIC CLOCKS; REGRESSION ANALYSIS;

CLOCK SIGNAL; MOS CIRCUITS; OPERATING FREQUENCY; PATH ANALYSIS; PATH SEARCH; TIMING CONSTRAINTS; TIMING PERFORMANCE; TIMING SIMULATORS;

TIMING CIRCUITS;

EID: 84989466311     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1982.1585562     Document Type: Conference Paper

References (13)

1. M. A. Wold, "Design verification and performance analysis," Proceedings of 15th Design Automation Conference, Las Vegas, Nevada, June 19-21, 1978, pp. 264-270.
2. J. D. Lesser and J. J. Shedletsky, "An experimental delay test generator for LSI logic," IEEE Transactions on Computers, Vol. C-29, pp. 235-248, March 1980.
3. A. Nãdas, "Random critical paths," Proceedings of IEEE International Symposium on Circuits and Systems, Houston, Texas, April 28-30, 1980, pp. 32-35.
4. T. M. McWilliams, "The SCALD timing verifier: A new approach to timing constraints in large digital systems," Proceedings of IEEE International Symposium on Circuits and Systems, Houston, Texas, April 28-30, 1980, pp. 415-423.
5. T. M. McWilliams, "Verification of timing constraints on large digital systems," Proceedings of 17th Design Automation Conference, Minneapolis, MN, June 23-25, 1980, pp. 139-147 (also J. Digital Systems, Vol. V, pp. 401-427, 1981).
6. J. McClure, "Frequency domain simulation of very large digital systems," Proceedings of IEEE International Symposium on Circuits and Systems, Houston, Texas, April 28-30, 1980, pp. 424-430.
7. B. G. Craft, "Statistical analysis techniques for predicting the delay variation of VLSI logic circuits," Proceedings of IEEE International Conference on Circuits and Computers, Port Chester, N.Y., October 1-3, 1980, pp. 574-577.
8. T. Sasaki, A. Yamada, T. Aoyama, K. Hasegawa, S. Kato, and S. Sato, "Hierarchical design verification for large digital systems," Proceeding of 18th Design Automation Conference, Nashville, TN, June 29-July 1, 1981, pp. 105-112.
9. R. Kamikawai, M. Yamada, and T. Chiba, "A critical path delay check system," Proceeding of 18th Design Automation Conference, Nashville, TN, June 28-July 1, 1981, pp. 118-123.
10. P. Ng, W. Glauert, and R. Kirk, "A timing verification system based on extracted MOS/VLSI circuit parameters," Proceedings of 18th Design Automation Conference, Nashville, TN, June 29-July 1, 1981, pp. 288-292.
11. D. W. McSweeney, "Timing verification of VLSI logic circuits," Proceedings of Conference on Advanced Research in VLSI, Cambridge, Mass., January 25-27, 1982, pp. 63-66. (Deaham, MA; Artech House, Inc.).
12. V. D. Agrawal, A. K. Bose, P. Kozak, H. N. Nham, and E. Pacas-Skewes, "A mixed-mode simulator," Proceedings of 17th Design Automation Conference, Minneapolis, MN, June 23-25, 1980, pp. 618-625 (also J. Digital Systems, Vol. V, pp. 383-400, 1981).
13. H. N. Nham and A. K. Bose, "A multiple delay simulator for MOS LSI circuits," Proceedings of 17th Design Automation Conference, Minneapolis, MN, June 23-25, 1980, pp. 610-617.