A simulator for at-speed robust testing of path delay faults in combinational circuits

IEEE Transactions on Computers

Volumn 45, Issue 11, 1996, Pages 1312-1318

  Hsu, Yuan Chieh ^a   Gupta, Sandeep K ^a  

^a University of Southern California ^*  (United States)

Author keywords

At speed delay testing; Delay testing; Fault simulation; Robust path delay testing

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; VECTORS;

AT SPEED ROBUST TESTING; FAULT SIMULATION; PATH DELAY FAULTS;

COMBINATORIAL CIRCUITS;

EID: 0030283411     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.544489     Document Type: Article

References (9)

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