Sequential logic path delay test generation by symbolic analysis

Proceedings of the Asian Test Symposium

Volumn , Issue , 1995, Pages 353-359

  Bose, Soumitra ^a   Agrawal, Vishwani D ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; ERROR DETECTION; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; SEQUENTIAL MACHINES; VECTORS;

BINARY DECISION DIAGRAMS; MULTIVALUED ALGEBRA; SEQUENTIAL LOGIC PATH DELAY TEST GENERATION; SYMBOLIC ANALYSIS; VALUE PROPAGATION RULE;

SEQUENTIAL CIRCUITS;

EID: 0029541923     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)