SCOPUS 정보 검색 플랫폼

Journal of Electronic Testing

Volumn 4, Issue 3, 1993, Pages 285-290

The optimistic update theorem for path delay testing in sequential circuits

(3) Bose, Soumitra a Agrawal, Prathima a Agrawal, Vishwani D a

a LUCENT TECHNOLOGIES (United States)

Author keywords

Fault simulation; path delay faults; test generation; timing analysis

Indexed keywords

ALGORITHMS; CRITICAL PATH ANALYSIS; DELAY CIRCUITS; ELECTRIC FAULT CURRENTS; ELECTRIC FAULT LOCATION; ELECTRIC NETWORK ANALYSIS; ERROR CORRECTION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; TIMING CIRCUITS; VECTORS;

FAULT COVERAGES; FAULT SIMULATION; PATH DELAY FAULTS; PATH DELAY TESTING; STATE VARIABLES; TEST GENERATION; TIMING ANALYSIS; UPDATE THEOREM;

SEQUENTIAL CIRCUITS;

EID: 0027646556 PISSN: 09238174 EISSN: 15730727 Source Type: Journal
DOI: 10.1007/BF00971977 Document Type: Article

Times cited : (7)

References (5)

1
- 84935532425
- T.J. Chakraborty, V.D. Agrawal, and M.L. Bushnell, “Path delay fault simulation algorithms for sequential circuits,”Proc. Asian Test Symp. pp. 52–56, November 1992.

2
- 84935542515
- I. Pomeranz, L.N. Reddy, and S.M. Reddy, “SPADES: a simulator for path delay faults in sequential circuits,”Proc. European Design Automation Conference, pp 428–435, September 1992.

3
- 84935599862
- G.L. Smith, “Model for delay faults based upon paths,”Proc. Inter. Test Conf., pp 342–349, September 1985.

4
- 84935566399
- S. Bose, P. Agrawal, and V.D. Agrawal, “A path delay fault simulator for sequential circuits,”Proc. Sixth Inter. Conf. on VLSI Design, pp 269–274, January 1993.

5
- 0026238696
- DYNAMITE: an efficient automatic test pattern generation system for path delay faults
- (1991) IEEE Trans. on Computer-Aided Design , vol.10 , pp. 1323-1335
- Fuchs, K.¹ Fink, F.² Schulz, E.S.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.