An extensible framework for multicore response time analysis

Real-Time Systems

Volumn 54, Issue 3, 2018, Pages 607-661

  Davis, Robert I ^a,b   Altmeyer, Sebastian ^c   Indrusiak, Leandro S ^a   Maiza, Claire ^d   Nelis, Vincent ^e   Reineke, Jan ^f  

^a UNIVERSITY OF YORK   (United Kingdom)

^b MOKAPLAN Inria Paris   (France)

^c UNIVERSITY OF AMSTERDAM   (Netherlands)

^d UNIV GRENOBLE ALPES   (France)

^e POLYTECHNIC INSTITUTE OF PORTO   (Portugal)

^f SAARLAND UNIVERSITY   (Germany)

Author keywords

Multicore scheduling; Timing analysis; Verification

Indexed keywords

CACHE MEMORY; DYNAMIC RANDOM ACCESS STORAGE; HARDWARE; MEMORY ARCHITECTURE; RESPONSE TIME (COMPUTER SYSTEMS); ROUTERS; SOFTWARE ARCHITECTURE; VERIFICATION;

ARCHITECTURAL COMPONENTS; CYCLE-ACCURATE SIMULATION; HARDWARE CONFIGURATIONS; MULTI CORE; MULTICORE ARCHITECTURES; REFERENCE ARCHITECTURE; RESPONSE-TIME ANALYSIS; TIMING ANALYSIS;

REAL TIME SYSTEMS;

EID: 85024505011     PISSN: 09226443     EISSN: 15731383     Source Type: Journal    
DOI: 10.1007/s11241-017-9285-4     Document Type: Article

References (89)

1. Alhammad A, Pellizzoni R (2014) Schedulability analysis of global memory-predictable scheduling. In: Proceedings of the international conference on embedded software (EMSOFT), pp 20:1–20:10
2. Alhammad A, Wasly S, Pellizzoni R (2015) Memory efficient global scheduling of real-time tasks. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 285–296
3. Altmeyer S (2013) Analysis of preemptively scheduled hard real-time systems. epubli GmbH. http://www.ebay.de/itm/Analysis-of-Preemptively-Scheduled-Hard-Real-time-Systems-Sebastian-Altmeyer-/142397905969
4. Altmeyer S, Burguière C (2009) A new notion of useful cache block to improve the bounds of cache-related preemption delay. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 109–118
5. Altmeyer S, Davis RI, Maiza C (2011) Cache related pre-emption aware response time analysis for fixed priority pre-emptive systems. In: Proceedings of the real-time systems symposium (RTSS), pp 261–271
6. Altmeyer S, Davis RI, Maiza C (2012) Improved cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems. Real-Time Syst 48(5):499–526
7. Altmeyer S, Douma R, Lunniss W, Davis RI (2014) Evaluation of cache partitioning for hard real-time systems. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 15–26
8. Altmeyer S, Davis RI, Indrusiak L, Maiza C, Nelis V, Reineke J (2015) A generic and compositional framework for multicore response time analysis. In: Proceedings of the international conference on real time networks and systems (RTNS), pp 129–138
9. Altmeyer S, Douma R, Lunniss W, Davis RI (2016) On the effectiveness of cache partitioning in hard real-time systems. Real-Time Syst. doi:10.1007/s11241-015-9246-8
10. Atanassov P, Puschner P (2001) Impact of DRAM refresh on the execution time of real-time tasks. In: IEEE international workshop on application of reliable computing and communication, pp 29–34
11. Audsley N, Burns A, Richardson M, Tindell K, Wellings AJ (1993) Applying new scheduling theory to static priority pre-emptive scheduling. Softw Eng J 8:284–292
12. Baker TP (1991) Stack-based scheduling for realtime processes. Real-Time Syst 3:67–99
13. Baruah S, Burns A (2006) Sustainable scheduling analysis. In: Proceedings of the real-time systems symposium (RTSS), pp 159–168
14. Bastoni A, Brandenburg B, Anderson J (2010) Cache-related preemption and migration delays: empirical approximation and impact on schedulability. In: Proceedings of the workshop on operating systems platforms for embedded real-time applications (OSPERT), pp 33–44
15. Bertogna M, Cirinei M (2007) Response-time analysis for globally scheduled symmetric multiprocessor platforms. In: Proceedings of the Real-Time Systems Symposium (RTSS), pp 149–160
16. Bhat B, Mueller F (2011) Making DRAM refresh predictable. Real-Time Syst 47(5):430–453
17. Bini E, Buttazzo G (2005) Measuring the performance of schedulability tests. Real-Time Syst 30:129–154
18. Binkert N et al (2011) The gem5 simulator. SIGARCH Comput Archit News 39(2):1–7
19. Blass T, Hahn S, Reineke J (2017) Write-back caches in WCET analysis. In: Proceedings of the euromicro conference on real-time systems (ECRTS)
20. Bril RJ, Altmeyer S, van den Heuvel MMHP, Davis RI, Behnam M (2014) Integrating cache-related pre-emption delays into analysis of fixed priority scheduling with pre-emption thresholds. In: Proceedings of the real-time systems symposium (RTSS), pp 161–172
21. Bril RJ, Altmeyer S, van den Heuvel MM, Davis RI, Behnam M (2017) Fixed priority scheduling with pre-emption thresholds and cache-related pre-emption delays: integrated analysis and evaluation. Real-Time Syst. doi:10.1007/s11241-016-9266-z
22. Bui D, Lee E, Liu I, Patel H, Reineke J (2011) Temporal isolation on multiprocessing architectures. In: Proceedings of the design automation conference (DAC), pp 274–279
23. Burns A, Wellings AJ (2013) A schedulability compatible multiprocessor resource sharing protocol—MRSP. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 282–291
24. Cai L, Gajski D (2003) Transaction level modeling: an overview. In: Proceedings of the international conference on hardware/software codesign and system synthesis (CODES), pp 19–24
25. Chattopadhyay S, Roychoudhury A, Mitra T (2010) Modeling shared cache and bus in multi-cores for timing analysis. In: Proceedings of the international workshop on software and compilers for embedded systems (SCOPES), pp 6:1–6:10
26. Choi J, Kang D, Ha S (2016) Conservative modeling of shared resource contention for dependent tasks in partitioned multi-core systems. In: Proceedings of design, automation, and test in Europe (DATE), pp 181–186
27. Dasari D, Nelis V, Akesson B (2016) A framework for memory contention analysis in multi-core platforms. Real-Time Syst 52(3):272–322
28. Davis RI, Burns A (2010) Improved priority assignment for global fixed priority pre-emptive scheduling in multiprocessor real-time systems. Real-Time Syst 47(1):1–40
29. Davis RI, Burns A, Marinho J, Nelis V, Petters SM, Bertogna M (2013) Global fixed priority scheduling with deferred pre-emption. In: Proceedings of the international conference on embedded and real-time computing systems and applications (RTCSA), pp 1–11
30. Davis RI, Burns A, Marinho J, Nelis V, Petters SM, Bertogna M (2015) Global and partitioned multiprocessor fixed priority scheduling with deferred preemption. ACM TECS 14(3):47:1–47:28
31. Davis RI, Altmeyer S, Reineke J (2016) Analysis of write-back caches under fixed-priority preemptive and non-preemptive scheduling. In: Proceedings of the international conference on real-time networks and systems (RTNS), pp 309–318
32. Falk H, Kleinsorge J (2009) Optimal static WCET-aware scratchpad allocation of program code. In: Proceedings of the design automation conference (DAC), pp 732–737
33. Ferdinand C, Wilhelm R (1999) Efficient and precise cache behavior prediction for real-time systems. Real-Time Syst 17(2–3):131–181
34. Ferdinand C, Martin F, Wilhelm R, Alt M (1999) Cache behavior prediction by abstract interpretation. Sci Comput Program 35(2–3):163–189
35. Gai P, Lipari G, Natale MD (2001) Minimizing memory utilization of real-time task sets in single and multi-processor systems-on-a-chip. In: Proceedings of the real-time systems symposium (RTSS), pp 73–83
36. Gustafsson J, Betts A, Ermedahl A, Lisper B (2010) The Mälardalen WCET benchmarks—past, present and future. In: Proceedings of the international workshop on worst-case execution time analysis (WCET), pp 137–147
37. Gustavsson A, Ermedahl A, Lisper B, Pettersson P (2010) Towards WCET analysis of multicore architectures using UPPAAL. In: Proceedings of the international workshop on worst-case execution time analysis (WCET), pp 101–112
38. Hahn S, Reineke J, Wilhelm R (2013) Towards compositionality in execution time analysis—definition and challenges. In: Proceedings of the international workshop on compositional theory and technology for real-time embedded systems (CRTS)
39. Hahn S, Reineke J, Wilhelm R (2015) Toward compact abstractions for processor pipelines. In: Proceedings of the correct system design—symposium in honor of Ernst-Rüdiger Olderog on the occasion of his 60th birthday, pp 205–220
40. Hahn S, Jacobs M, Reineke J (2016) Enabling compositionality for multicore timing analysis. In: Proceedings of the international conference on real time and networks systems (RTNS)
41. Huang WH, Chen JJ, Reineke J (2016) MIRROR: symmetric timing analysis for real-time tasks on multicore platforms with shared resources. In: Proceedings of the design automation conference (DAC), pp 1–6
42. Jacobs M, Hahn S, Hack S (2016) A framework for the derivation of WCET analyses for multi-core processors. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 141–151
43. Joseph M, Pandya P (1986) Finding response times in a real-time system. Comput J 29(5):390–395
44. Kelter T, Falk H, Marwedel P, Chattopadhyay S, Roychoudhury A (2011) Bus-aware multicore WCET analysis through TDMA offset bounds. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 3–12
45. Kelter T, Falk H, Marwedel P, Chattopadhyay S, Roychoudhury A (2014) Static analysis of multi-core TDMA resource arbitration delays. Real-Time Syst J 50(2):185–229
46. Kim H, de Niz D, Andersson B, Klein M, Mutlu O, Rajkumar R (2014a) Bounding memory interference delay in COTS-based multi-core systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 145–154
47. Kim Y, Broman D, Cai J, Shrivastaval A (2014b) Wcet-aware dynamic code management on scratchpads for software-managed multicores. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 179–188
48. Kim H, de Niz D, Andersson B, Klein M, Mutlu O, Rajkumar R (2016) Bounding and reducing memory interference in cots-based multi-core systems. Real-Time Syst 52(3):356–395
49. Lampka K, Giannopoulou G, Pellizzoni R, Wu Z, Stoimenov N (2014) A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets. Real-Time Syst 50(5–6):736–773
50. Lee CG, Hahn J, Seo YM, Min S, Ha R, Hong S, Park CY, Lee M, Kim CS (1998) Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Trans Comput 47(6):700–713
51. Lee C, Lee K, Hahn J, Seo YM, Min SL, Ha R, Hong S, Park CY, Lee M, Kim CS (2001) Bounding cache-related preemption delay for real-time systems. IEEE Trans Softw Eng 27(9):805–826
52. Li YTS, Malik S (1995) Performance analysis of embedded software using implicit path enumeration. In: Proceedings of the design automation conference (DAC), pp 456–461
53. Li L, Mayer A (2016) Trace-based analysis methodology of program flash contention in embedded multicore systems. In: Proceedings of design, automation, and test in Europe (DATE), pp 199–204
54. Li Y, Suhendra V, Liang Y, Mitra T, Roychoudhury A (2009a) Timing analysis of concurrent programs running on shared cache multi-cores. In: Proceedings of the real-time systems symposium (RTSS), pp 57–67
55. Li Y, Suhendra V, Liang Y, Mitra T, Roychoudhury A (2009b) Timing analysis of concurrent programs running on shared cache multi-cores. In: Proceedings of the real-time systems symposium, pp 57–67
56. Liu I, Reineke J, Broman D, Zimmer M, Lee EA (2012) A PRET microarchitecture implementation with repeatable timing and competitive performance. In: Proceeedings of the international conference on computer design (ICCD), pp 87–93
57. Lu J, Bai K, Shrivastava A (2013) Ssdm: Smart stack data management for software managed multicores (SMMS). In: Proceedings of the design automation conference (DAC), pp 1–8
58. Lundqvist T, Stenström P (1999) Timing anomalies in dynamically scheduled microprocessors. In: Proceedings of the real-time systems symposium (RTSS), pp 12–21
59. Lunniss W, Altmeyer S, Davis RI (2012) Optimising task layout to increase schedulability via reduced cache related pre-emption delays. In: Proceedings of the international conference on real-time networks and systems (RTNS), pp 161–170
60. Lunniss W, Altmeyer S, Maiza C, Davis R (2013) Integrating cache related pre-emption delay analysis into EDF scheduling. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 75–84
61. Lv M, Yi W, Guan N, Yu G (2010) Combining abstract interpretation with model checking for timing analysis of multicore software. In: Proceedings of the real-time systems symposium (RTSS), pp 339–349
62. Mancuso R, Dudko R, Betti E, Cesati M, Caccamo M, Pellizzoni R (2013) Real-time cache management framework for multi-core architectures. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 45–54
63. Melani A, Bertogna M, Bonifaci V, Marchetti-Spaccamela A, Buttazzo G (2015) Memory-processor co-scheduling in fixed priority systems. In: Proceedings of the international conference on real-time networks and systems (RTNS), pp 87–96
64. Melani A, Bertogna M, Davis RI, Bonifaci V, Marchetti-Spaccamela A, Buttazzo G (2016) Exact response time analysis for fixed priority memory-processor co-scheduling. IEEE Trans Comput. doi:10.1109/TC.2016.2614819
65. Micron Technologies, Inc (1999) Various methods of DRAM refresh. Tech. rep
66. Muliadi L (1999) Discrete event modeling in ptolemy II. Master’s report, University of California, Berkeley. http://ptolemy.eecs.berkeley.edu/publications/papers/99/deModeling/
67. Nowotsch J, Paulitsch M, Buhler D, Theiling H, Wegener S, Schmidt M (2014) Multi-core interference-sensitive WCET analysis leveraging runtime resource capacity enforcement. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 109–118
68. Paolieri M, Quiñones E, Cazorla FJ, Bernat G, Valero M (2009) Hardware support for WCET analysis of hard real-time multicore systems. SIGARCH Comput Archit News 37(3):57–68
69. Paolieri M, Quiñones E, Cazorla FJ, Davis RI, Valero M (2011) Ia ^ 3: An interference aware allocation algorithm for multicore hard real-time systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 280–290
70. Pellizzoni R, Schranzhofer A, Chen JJ, Caccamo M, Thiele L (2010) Worst case delay analysis for memory interference in multicore systems. In: Proceedings of design automation and test in Europe (DATE), pp 741–746
71. Pellizzoni R, Betti E, Bak S, Criswell J, Caccamo M, Kegley R (2011) A predictable execution model for COTS-based embedded systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 269–279
72. Radojković P, Girbal S, Grasset A, Quiñones E, Yehia S, Cazorla FJ (2012) On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments. ACM TACO 8(4):34
73. Reineke J, Doerfert J (2014) Architecture-parametric timing analysis. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 189–200. doi:10.1109/RTAS.2014.6926002
74. Rihani H, Moy M, Maiza C, Davis RI, Altmeyer S (2016) Response time analysis of synchronous data flow programs on a many-core processor. In: Proceedings of the international conference on real-time networks and systems (RTNS), ACM, pp 67–76
75. Rosen J, Andrei A, Eles P, Peng Z (2007) Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip. In: proceedings of the real-time systems symposium (RTSS), pp 49–60
76. Schliecker S, Negrean M, Ernst R (2010) Bounding the shared resource load for the performance analysis of multiprocessor systems. In: Proceedings of the design automation conference (DAC), pp 759–764
77. Schranzhofer A, Chen JJ, Thiele L (2010) Timing analysis for TDMA arbitration in resource sharing systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 215–224
78. Schranzhofer A, Pellizzoni R, Chen JJ, Thiele L, Caccamo M (2011) Timing analysis for resource access interference on adaptive resource arbiters. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 213–222
79. Slijepcevic M, Kosmidis L, Abella J, Quiones E, Cazorla FJ (2014) Time-analysable non-partitioned shared caches for real-time multicore systems. In: Proceedings of the design automation conference (DAC), pp 1–6
80. Trilla D, Jalle J, Fernandez M, Abella J, Cazorla FJ (2016) Improving early design stage timing modeling in multicore based real-time systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 1–12
81. Valsan PK, Yun H, Farshchi F (2016) Taming non-blocking caches to improve isolation in multicore real-time systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 1–12
82. Ward BC, Herman JL, Kenna CJ, Anderson JH (2013) Making shared caches more predictable on multicore platforms. In: Proceedings of the euromicro conference on real-time systems, pp 157–167
83. Wasly S, Pellizzoni R (2014) Hiding memory latency using fixed priority scheduling. In: Proceedings of the IEEE real-time and embedded technology and applications symposium (RTAS), pp 75–86
84. Whitham J, Davis RI, Audsley N, Altmeyer S, Maiza C (2012) Investigation of scratchpad memory for preemptive multitasking. In: Proceedings of the real-time systems symposium (RTSS), pp 3–13
85. Whitham J, Audsley N, Davis RI (2014) Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system. ACM Trans Embed Comput Syst 13(4s):120:1–120:25
86. Yan J, Zhang W (2008) WCET analysis for multi-core processors with shared L2 instruction caches. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 80–89
87. Yao G, Pellizzoni R, Bak S, Betti E, Caccamo M (2012) Memory-centric scheduling for multicore hard real-time systems. Real-Time Syst J 48(6):681–715
88. Yun H, Yao G, Pellizzoni R, Caccamo M, Sha L (2012) Memory access control in multiprocessor for real-time systems with mixed criticality. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 299–308
89. Yun H, Pellizzoni R, Valsan PK (2015) Parallelism-aware memory interference delay analysis for COTS multicore systems. In: Proceedings of the euromicro conference on real-time Systems, pp 184–195