Trace-based analysis methodology of program flash contention in embedded multicore systems

Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016

Volumn , Issue , 2016, Pages 199-204

  Li, Lin ^a   Mayer, Albrecht ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; REAL TIME SYSTEMS; TRACE ANALYSIS;

EMBEDDED MULTICORE; HARD REAL-TIME; MULTI-CORE SYSTEMS; PERFORMANCE IMPACT; PERFORMANCE ISSUES; POST PROCESSING; REAL TIME PERFORMANCE; SHARED RESOURCES;

MULTICORE PROGRAMMING;

EID: 84973645507     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.3850/9783981537079_0442     Document Type: Conference Paper

References (15)

1. C. Park, J. Seo, D. Seo, S. Kim, and B. Kim, "Cost-efficient memory architecture design of nand flash memory embedded systems," Computer Design, 2003. Proceedings. 21st International Conference on, pp. 474-480, 2003.
2. Infineon, "AURIX Family-TC29xT," http://www.infineon.com/ cms/en/product/microcontroller/32-bit-tricore-tm-microcontroller/ aurix-tm-family/aurix-tm-family-%E2%80%93-tc29xt/channel.html? channel=db3a304342c787030142dc92c9aa1674, [Online; accessed 20-August-2015].
3. S. Zhuravlev, S. Blagodurov, and A. Fedorova, "Addressing shared resource contention in multicore processors via scheduling," ACM SIGARCH Computer Architecture News, vol. 38, no. 1, pp. 129-142, 2010.
4. K. Lu, D. Muller-Gritschneder, and U. Schlichtmann, "Analytical timing estimation for temporally decoupled tlms considering resource conflicts," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, pp. 1161-1166, 2013.
5. K. Lampka, G. Giannopoulou, R. Pellizzoni, Z. Wu, and N. Stoimenov, "A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets," Real-Time Systems, vol. 50, no. 5-6, pp. 736-773, 2014.
6. R. Hood, H. Jin, P. Mehrotra, J. Chang, J. Djomehri, S. Gavali, D. Jespersen, K. Taylor, and R. Biswas, "Performance impact of resource contention in multicore systems," Parallel & Distributed Processing (IPDPS), 2010 IEEE International Symposium on, pp. 1-12, 2010.
7. R. Pellizzoni, A. Schranzhofer, J.-J. Chen, M. Caccamo, and L. Thiele, "Worst case delay analysis for memory interference in multicore systems," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, pp. 741-746, 2010.
8. L. Liu, Z. Li, and A. H. Sameh, "Analyzing memory access intensity in parallel programs on multicore," Proceedings of the 22nd annual international conference on Supercomputing, pp. 359-367, 2008.
9. S. Blagodurov, S. Zhuravlev, and A. Fedorova, "Contention-aware scheduling on multicore systems," ACM Transactions on Computer Systems (TOCS), vol. 28, no. 4, p. 8, 2010.
10. F. Pinel, J. E. Pecero, P. Bouvry, and S. U. Khan, "Memory-aware green scheduling on multi-core processors," Parallel Processing Workshops (ICPPW), 2010 39th International Conference on, pp. 485-488, 2010.
11. Z. Majo and T. R. Gross, "Memory management in numa multicore systems: trapped between cache contention and interconnect overhead," ACM SIGPLAN Notices, vol. 46, no. 11, pp. 11-20, 2011.
12. S. Chattopadhyay, A. Roychoudhury, and T. Mitra, "Modeling shared cache and bus in multi-cores for timing analysis," Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems, p. 6, 2010.
13. A. Mayer, H. Siebert, and K. D. McDonald-Maier, "Debug support, calibration and emulation for multiple processor and powertrain control socs," Proceedings of the conference on Design, Automation and Test in Europe-Volume 3, pp. 148-152, 2005.
14. A. Mayer, "A seamless tool access architecture from esl to end product," System, Software, SoC and Silicon Debug Conference (S4D), 2009.
15. Wikipedia, "Dhrystone," https://en.wikipedia.org/wiki/Dhrystone, [Online; accessed 20-August-2015].