Timing anomalies in dynamically scheduled microprocessors

Proceedings - Real-Time Systems Symposium

Volumn , Issue , 1999, Pages 12-21

  Lundqvist, Thomas ^a   Stenstrom, Per ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; SCHEDULING;

CACHING; WORST CASE EXECUTION TIME;

REAL TIME SYSTEMS;

EID: 0033337990     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)