Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems

2016 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2016 - Proceedings

Volumn , Issue , 2016, Pages

  Trilla, David ^a,b   Jalle, Javier ^a,b   Fernandez, Mikel ^a   Abella, Jaume ^a   Cazorla, Francisco J ^a,c  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c ARTIFICIAL INTELLIGENCE RESEARCH INSTITUTE IIIA CSIC   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; BUDGET CONTROL; DESIGN; EMBEDDED SYSTEMS; INTERACTIVE COMPUTER SYSTEMS;

ASSOCIATED COSTS; COMPUTING PLATFORM; EARLY DESIGN PHASIS; EARLY DESIGN STAGES; MULTI-CORE PROCESSOR; REAL-TIME EMBEDDED SYSTEMS; SOFTWARE SUPPLIERS; SYSTEM INTEGRATORS;

REAL TIME SYSTEMS;

EID: 84971261002     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2016.7461338     Document Type: Conference Paper

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