Transaction Level Modeling: An Overview

Hardware/Software Codesign - Proceedings of the International Workshop

Volumn , Issue , 2003, Pages 19-24

  Gai, Lukai ^a   Gajski, Daniel ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Exploration; Modeling; Refinement; Synthesis; Transaction level model; Validation

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTATIONAL METHODS; COMPUTER OPERATING SYSTEMS; COMPUTER SIMULATION; DATA FLOW ANALYSIS; DIGITAL STORAGE; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; OBJECT ORIENTED PROGRAMMING; REAL TIME SYSTEMS; SHIFT REGISTERS; SYSTEMS ANALYSIS;

INSTRUCTION SET SIMULATION (ISS); REGISTER TRANSFER LEVEL (RTL); SYSTEMS EXPLORATION; SYSTEMS REFINEMENT; SYSTEMS SYNTHESIS; SYSTEMS VALIDATION; TRANSACTION LEVEL MODELS (TLM);

COMPUTER ARCHITECTURE;

EID: 1142299899     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. CoWare home page (www.coware.com).
2. OSCI home page (www.systemc.org).
3. STOC home page (www.specc.org).
4. The SystemC Verification Standard, version 1.0 (www.systemc.org).
5. VCC home page (www.cadence.com/products/vcc.html).
6. S. Abdi et al. System-On-Chip Environment (SCE): Tutorial. Technical Report CECS-TR-02-28, UCI, Sept 2002.
7. S. Abdi et al. Formal Verification of Specification Partitioning. Technical Report CECS-TR-03-06, UCI, Mar 2003.
8. L. Cai et al. Comparison of SpecC and SystemC Languages for System Design. Technical Report CECS-TR-03-11, UCI, May 2003.
9. W. Cesario et al. Multiprocessor SoC Platforms: a Component-Based Design Approach. In IEEE Trans. on Design and Test, Nov-Dec 2002.
10. D. Gajski et al. SpecC: Specification Language and Methodology. Kluwer, Jan 2000.
11. P. Gerin et al. Scalable and Flexible Cosimulation of SoC Designs with Heterogeneous Multi-Processor Target Architectures. In ASPDAC, 2001.
12. T. Grotker et al. System Design with SystemC. Kluwer, 2002.
13. K. Keutzer et al. System Level Design: Orthogonalization of Concerns and Platform-Based Design. IEEE Trans. on CAD, Dec 2000.
14. S. Pasricha. Transaction Level Modelling of SoC with SystemC 2.0. In Synopsys User Group Conference, 2002.
15. P. Paulin et al. StepNP: A System-Level Exploration Platform for Network Processors. In IEEE Trans. on Design and Test, Nov-Dec 2002.
16. N. Pazos et al. System Level Performance Estimation. In SystemC Methodologies and Applications. Kluwer, 2003.