Exact Response Time Analysis for Fixed Priority Memory-Processor Co-Scheduling

IEEE Transactions on Computers

Volumn 66, Issue 4, 2017, Pages 631-646

  Melani, Alessandra ^a   Bertogna, Marko ^b   Davis, Robert I ^c,d   Bonifaci, Vincenzo ^e   Marchetti Spaccamela, Alberto ^f   Buttazzo, Giorgio ^a  

^a SCUOLA SUPERIORE SANT ANNA   (Italy)

^b UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^c UNIVERSITY OF YORK   (United Kingdom)

^d INRIA Paris   (France)

^e CNR   (Italy)

^f SAPIENZA UNIVERSITY OF ROME   (Italy)

Author keywords

Co scheduling; real time systems; response time analysis; schedulability analysis

Indexed keywords

BANDWIDTH; INTEGRATED CIRCUIT DESIGN; INTERACTIVE COMPUTER SYSTEMS; REAL TIME SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); SCHEDULING;

CO-SCHEDULING; POLYNOMIAL COMPLEXITY; PROCESSOR UTILIZATION; RESPONSE-TIME ANALYSIS; SCHEDULABILITY ANALYSIS; SPORADIC REAL-TIME TASKS; TECHNOLOGICAL ADVANCES; THEORETICAL FRAMEWORK;

SCHEDULING ALGORITHMS;

EID: 85015638085     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2016.2614819     Document Type: Article

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