Hiding memory latency using fixed priority scheduling

Real-Time Technology and Applications - Proceedings

Volumn 2014-October, Issue October, 2014, Pages 75-85

  Wasly, Saud ^a,b   Pellizzoni, Rodolfo ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

^b KING ABDULAZIZ UNIVERSITY   (Saudi Arabia)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; DYNAMIC RANDOM ACCESS STORAGE; INTERACTIVE COMPUTER SYSTEMS; PSYCHOPHYSIOLOGY; SCHEDULING;

DYNAMIC SCHEDULING ALGORITHMS; EMBEDDED PLATFORMS; FIXED PRIORITY SCHEDULING; HIDING MEMORY LATENCY; MULTI PROCESSOR SYSTEMS; PROCESSOR EXECUTION; PROCESSOR UTILIZATION; SPORADIC REAL-TIME TASKS;

REAL TIME SYSTEMS;

EID: 84937557787     PISSN: 10801812     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2014.6925992     Document Type: Conference Paper

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