Temporal isolation on multiprocessing architectures

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 274-279

  Bui, Dai ^a   Lee, Edward ^a   Liu, Isaac ^a   Patel, Hiren ^b   Reineke, Jan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF WATERLOO   (Canada)

Author keywords

instruction set architecture; memory hierarchy; microarchitecture; network on chip; pipelines; Precision timed architectures; PRET machines

Indexed keywords

APPLICATION PROGRAMS; COMPUTER AIDED DESIGN; EMBEDDED SYSTEMS; NETWORK ARCHITECTURE; NETWORK-ON-CHIP; PIPELINES;

CYBER PHYSICAL SYSTEMS (CPSS); INSTRUCTION SET ARCHITECTURE; MEMORY HIERARCHY; MICRO ARCHITECTURES; ON CHIP COMMUNICATION; SIMULTANEOUS MULTI-THREADING; SYMMETRIC MULTI PROCESSING; TEMPORAL ISOLATION;

MEMORY ARCHITECTURE;

EID: 80052658532     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2024724.2024787     Document Type: Conference Paper

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