-
1
-
-
47649131240
-
Predictable implementation of real-time applications on multiprocessor systems-on-chip
-
A. Andrei, P. Eles, Z. Peng, and J. Rosen. Predictable implementation of real-time applications on multiprocessor systems-on-chip. In VLSID, pages 103-110, 2008.
-
(2008)
VLSID
, pp. 103-110
-
-
Andrei, A.1
Eles, P.2
Peng, Z.3
Rosen, J.4
-
3
-
-
70350060171
-
Time and memory tradeoffs in the implementation of AUTOSAR components
-
Apr
-
A. Ferrari, M. D. Natale, G. Gentile, G. Reggiani, and P. Gai. Time and memory tradeoffs in the implementation of AUTOSAR components. In DATE, pages 864-869, Apr 2009.
-
(2009)
DATE
, pp. 864-869
-
-
Ferrari, A.1
Natale, M.D.2
Gentile, G.3
Reggiani, G.4
Gai, P.5
-
4
-
-
0014477093
-
Bounds on multiprocessing timing anomalies
-
R. Graham. Bounds on multiprocessing timing anomalies. SIAM Journal on Applied Mathematics, 17:263-269, 1969.
-
(1969)
SIAM Journal on Applied Mathematics
, vol.17
, pp. 263-269
-
-
Graham, R.1
-
5
-
-
0010338549
-
Bounds on the performance of scheduling algorithms
-
John Wiley and Sons
-
R. Graham. Bounds on the performance of scheduling algorithms. In Computer and Job Scheduling Theory, pages 165-227. John Wiley and Sons, 1976.
-
(1976)
Computer and Job Scheduling Theory
, pp. 165-227
-
-
Graham, R.1
-
6
-
-
72249098329
-
Cache-aware scheduling and analysis for multi-cores
-
October
-
N. Guan, M. Stigge, W. Yi, and G. Yu. Cache-aware scheduling and analysis for multi-cores. In EMSOFT, pages 245-254, October 2009.
-
(2009)
EMSOFT
, pp. 245-254
-
-
Guan, N.1
Stigge, M.2
Yi, W.3
Yu, G.4
-
7
-
-
77649293394
-
Timing analysis of concurrent programs running on shared cache multi-cores
-
Y. Li, V. Suhendra, Y. Liang, T. Mitra, and A. Roychoudhury. Timing analysis of concurrent programs running on shared cache multi-cores. In RTSS, 2009.
-
(2009)
RTSS
-
-
Li, Y.1
Suhendra, V.2
Liang, Y.3
Mitra, T.4
Roychoudhury, A.5
-
8
-
-
70350060182
-
Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources
-
April
-
M. Negrean, S. Schliecker, and R. Ernst. Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources. In DATE, pages 524-529, April 2009.
-
(2009)
DATE
, pp. 524-529
-
-
Negrean, M.1
Schliecker, S.2
Ernst, R.3
-
9
-
-
67249152411
-
Coscheduling of CPU and I/O transactions in cots-based embedded systems
-
Dec
-
R. Pellizzoni, B. D. Bui, M. Caccamo, and L. Sha. Coscheduling of CPU and I/O transactions in COTS-based embedded systems. In RTSS, pages 221-231, Dec 2008.
-
(2008)
RTSS
, pp. 221-231
-
-
Pellizzoni, R.1
Bui, B.D.2
Caccamo, M.3
Sha, L.4
-
10
-
-
76549093841
-
Impact of peripheralprocessor interference on WCET analysis of real-time embedded systems
-
March
-
R. Pellizzoni and M. Caccamo. Impact of peripheralprocessor interference on WCET analysis of real-time embedded systems. IEEE TOC, pages 400-415, March 2010.
-
(2010)
IEEE TOC
, pp. 400-415
-
-
Pellizzoni, R.1
Caccamo, M.2
-
11
-
-
48649100636
-
Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip
-
J. Rosen, A. Andrei, P. Eles, and Z. Peng. Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip. In RTSS, pages 49-60, 2007.
-
(2007)
RTSS
, pp. 49-60
-
-
Rosen, J.1
Andrei, A.2
Eles, P.3
Peng, Z.4
-
12
-
-
34547181873
-
Integrated analysis of communicating tasks in MPSOCS
-
S. Schliecker, M. Ivers, and R. Ernst. Integrated analysis of communicating tasks in MPSoCs. In CODES+ISSS, pages 288-293, 2006.
-
(2006)
CODES+ISSS
, pp. 288-293
-
-
Schliecker, S.1
Ivers, M.2
Ernst, R.3
-
13
-
-
63349110729
-
Reliable performance analysis of a multicore multithreaded system-on-chip
-
S. Schliecker, M. Negrean, G. Nicolescu, P. Paulin, and R. Ernst. Reliable performance analysis of a multicore multithreaded system-on-chip. In CODES/ISSS, pages 161-166, 2008.
-
(2008)
CODES/ISSS
, pp. 161-166
-
-
Schliecker, S.1
Negrean, M.2
Nicolescu, G.3
Paulin, P.4
Ernst, R.5
-
14
-
-
0033750056
-
Fast and precise WCET prediction by separate cache and path analyses
-
May
-
H. Theiling, C. Ferdinand, and R. Wilhelm. Fast and precise WCET prediction by separate cache and path analyses. Real-Time Systems, 18(2/3), May 2000.
-
(2000)
Real-time Systems
, vol.18
, Issue.2-3
-
-
Theiling, H.1
Ferdinand, C.2
Wilhelm, R.3
-
15
-
-
0028383503
-
Scheduling multiple variable-speed machines
-
M. A. Trick. Scheduling multiple variable-speed machines. Operations Research, 42:234-248, 1994.
-
(1994)
Operations Research
, vol.42
, pp. 234-248
-
-
Trick, M.A.1
-
16
-
-
67650862807
-
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
-
July
-
R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand. Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-critical Embedded Systems. TCAD, 28(7):966-978, July 2009.
-
(2009)
TCAD
, vol.28
, Issue.7
, pp. 966-978
-
-
Wilhelm, R.1
Grund, D.2
Reineke, J.3
Schlickling, M.4
Pister, M.5
Ferdinand, C.6
-
17
-
-
51249094583
-
WCET analysis for multi-core processors with shared L2 instruction caches
-
J. Yan and W. Zhang. WCET analysis for multi-core processors with shared L2 instruction caches. In RTAS, pages 80-89, 2008.
-
(2008)
RTAS
, pp. 80-89
-
-
Yan, J.1
Zhang, W.2
|