-
6
-
-
84871304485
-
Multicores and critical systems: Challenges for temporal analysability
-
C. Rochange and P. Sainrat, "Multicores and critical systems: Challenges for temporal analysability," SAE AeroTech, 2011.
-
(2011)
SAE AeroTech
-
-
Rochange, C.1
Sainrat, P.2
-
10
-
-
79957583292
-
A predictable execution model for COTS-based embedded systems
-
R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, and R. Kegley, "A predictable execution model for COTS-based embedded systems," 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011.
-
(2011)
17th IEEE Real-Time and Embedded Technology and Applications Symposium
-
-
Pellizzoni, R.1
Betti, E.2
Bak, S.3
Yao, G.4
Criswell, J.5
Caccamo, M.6
Kegley, R.7
-
11
-
-
84857392612
-
Deterministic execution model on COTS hardware
-
F. Boniol, H. Cassé, E. Noulard, and C. Pagetti, "Deterministic execution model on COTS hardware," 25st Int. Conf. on Architecture of Computing Systems, 2012.
-
(2012)
25st Int. Conf. on Architecture of Computing Systems
-
-
Boniol, F.1
Cassé, H.2
Noulard, E.3
Pagetti, C.4
-
12
-
-
84907892109
-
Evaluation of resource arbitration methods for multi-core real-time systems
-
T. Kelter, T. Harde, P. Marwedel, and H. Falk, "Evaluation of resource arbitration methods for multi-core real-time systems," 13th Int. Workshop on Worst-Case Execution time Analysis, 2013.
-
(2013)
13th Int. Workshop on Worst-Case Execution Time Analysis
-
-
Kelter, T.1
Harde, T.2
Marwedel, P.3
Falk, H.4
-
14
-
-
77649293394
-
Timing analysis of concurrent programs running on shared cache multi-cores
-
Y. Li, V. Suhendra, Y. Liang, T. Mitra, and A. Roychoudhury, "Timing analysis of concurrent programs running on shared cache multi-cores," 30th IEEE Real-Time Systems Symposium, 2009.
-
(2009)
30th IEEE Real-Time Systems Symposium
-
-
Li, Y.1
Suhendra, V.2
Liang, Y.3
Mitra, T.4
Roychoudhury, A.5
-
15
-
-
77649302111
-
Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches
-
D. Hardy, T. Piquet, and I. Puaut, "Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches," 30th IEEE Real-Time Systems Symposium, 2009.
-
(2009)
30th IEEE Real-Time Systems Symposium
-
-
Hardy, D.1
Piquet, T.2
Puaut, I.3
-
17
-
-
80052979914
-
Bus-aware multicore WCET analysis through TDMA offset bounds
-
T. Kelter, H. Falk, P. Marwedel, S. Chattopadhyay, and A. Roychoudhury, "Bus-aware multicore WCET analysis through TDMA offset bounds," 23rd Euromicro Conf. on Real-Time Systems, 2011.
-
(2011)
23rd Euromicro Conf. on Real-Time Systems
-
-
Kelter, T.1
Falk, H.2
Marwedel, P.3
Chattopadhyay, S.4
Roychoudhury, A.5
-
18
-
-
84862001438
-
A unified WCET analysis framework for multi-core platforms
-
S. Chattopadhyay, C. L. Kee, A. Roychoudhury, T. Kelter, P. Marwedel, and H. Falk, "A unified WCET analysis framework for multi-core platforms," 18th Real Time and Embedded Technology and Applications Symposium, 2012.
-
(2012)
18th Real Time and Embedded Technology and Applications Symposium
-
-
Chattopadhyay, S.1
Kee, C.L.2
Roychoudhury, A.3
Kelter, T.4
Marwedel, P.5
Falk, H.6
-
19
-
-
48649100636
-
Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip
-
J. Rosen, A. Andrei, P. Eles, and Z. Peng, "Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip," 28th IEEE Int. Real-Time Systems Symposium, 2007.
-
(2007)
28th IEEE Int. Real-Time Systems Symposium
-
-
Rosen, J.1
Andrei, A.2
Eles, P.3
Peng, Z.4
-
20
-
-
70450235469
-
Hardware support for WCET analysis of hard real-time multicore systems
-
M. Paolieri, F. J. Cazorla, M. Valero, and G. Bernat, "Hardware support for WCET analysis of hard real-time multicore systems," 36th Annual Int. Symposium on Computer Architecture, 2009.
-
(2009)
36th Annual Int. Symposium on Computer Architecture
-
-
Paolieri, M.1
Cazorla, F.J.2
Valero, M.3
Bernat, G.4
-
21
-
-
77953112504
-
Bounding the shared resource load for the performance analysis of multiprocessor systems
-
S. Schliecker, M. Negrean, and R. Ernst, "Bounding the shared resource load for the performance analysis of multiprocessor systems," Design, Automation & Test in Europe Conference & Exhibition, 2010.
-
(2010)
Design, Automation & Test in Europe Conference & Exhibition
-
-
Schliecker, S.1
Negrean, M.2
Ernst, R.3
-
22
-
-
84862958680
-
Response time analysis of COTS-based multicores considering the contention on the shared memory bus
-
D. Dasari, B. Andersson, V. Nelis, S. M. Petters, A. Easwaran, and J. Lee, "Response time analysis of COTS-based multicores considering the contention on the shared memory bus," 10th IEEE Int. Conf. on Trust, Security and Privacy in Computing and Communications, 2011.
-
(2011)
10th IEEE Int. Conf. on Trust, Security and Privacy in Computing and Communications
-
-
Dasari, D.1
Andersson, B.2
Nelis, V.3
Petters, S.M.4
Easwaran, A.5
Lee, J.6
-
24
-
-
0347747028
-
Process cruise control: Throttling memory access in a soft real-time environment
-
University of Erlangen
-
F. Bellosa, "Process cruise control: Throttling memory access in a soft real-time environment," University of Erlangen, Tech. Rep., 1997.
-
(1997)
Tech. Rep.
-
-
Bellosa, F.1
-
25
-
-
84903837362
-
Memory access-The third dimension of scheduling
-
University of Erlangen
-
-, "Memory access-the third dimension of scheduling," University of Erlangen, Tech. Rep., 1997.
-
(1997)
Tech. Rep.
-
-
Bellosa, F.1
-
26
-
-
84866464961
-
Memory access control in multiprocessor for real-time systems with mixed criticality
-
H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha, "Memory access control in multiprocessor for real-time systems with mixed criticality," 24th Euromicro Conf. on Real-Time Systems, 2012.
-
(2012)
24th Euromicro Conf. on Real-Time Systems
-
-
Yun, H.1
Yao, G.2
Pellizzoni, R.3
Caccamo, M.4
Sha, L.5
-
27
-
-
84928639565
-
Multi-core composability in the face of memory-bus contention
-
M. Behnam, R. Inam, T. Nolte, and M. Sjödin, "Multi-core composability in the face of memory-bus contention," 5th Int. Workshop on Compositional Theory and Technology for Real-Time Embdedded Systems, 2012.
-
(2012)
5th Int. Workshop on Compositional Theory and Technology for Real-Time Embdedded Systems
-
-
Behnam, M.1
Inam, R.2
Nolte, T.3
Sjödin, M.4
-
29
-
-
67249083022
-
System considerations for robust time and space partitioning in integrated modular avionics
-
J. Littlefield-Lawwill and L. Kinnan, "System considerations for robust time and space partitioning in integrated modular avionics," 27th Digital Avionics Systems Conf., 2008.
-
(2008)
27th Digital Avionics Systems Conf.
-
-
Littlefield-Lawwill, J.1
Kinnan, L.2
-
30
-
-
84903845867
-
DOT/FAA/AR-11/2-handbook of the selection and evaluation of microprocessors for airborne systems
-
B. Green, J. Marotta, B. Petre, K. Lillestolen, R. Spencer, N. Gupta, D. O'Leary, J. Lee, J. Strasburger, A. Nordsieck, B. Manners, and R. Mahapatra, "DOT/FAA/AR-11/2-handbook of the selection and evaluation of microprocessors for airborne systems," FAA, Tech. Rep., 2011.
-
(2011)
FAA, Tech. Rep.
-
-
Green, B.1
Marotta, J.2
Petre, B.3
Lillestolen, K.4
Spencer, R.5
Gupta, N.6
O'leary, D.7
Lee, J.8
Strasburger, J.9
Nordsieck, A.10
Manners, B.11
Mahapatra, R.12
-
31
-
-
0002697007
-
Reliable and precise WCET determination for a real-life processor
-
C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, and R. Wilhelm, "Reliable and precise WCET determination for a real-life processor," EMSOFT 2001, First Workshop on Embedded Software, 2001.
-
(2001)
EMSOFT 2001, First Workshop on Embedded Software
-
-
Ferdinand, C.1
Heckmann, R.2
Langenbach, M.3
Martin, F.4
Schmidt, M.5
Theiling, H.6
Thesing, S.7
Wilhelm, R.8
-
33
-
-
0032292381
-
Combining abstract interpretation and ILP for microarchitecture modelling and program path analysis
-
H. Theiling and C. Ferdinand, "Combining abstract interpretation and ILP for microarchitecture modelling and program path analysis," 19th IEEE Real-Time Systems Symposium, 1998.
-
(1998)
19th IEEE Real-Time Systems Symposium
-
-
Theiling, H.1
Ferdinand, C.2
-
35
-
-
38849129464
-
A definition and classification of timing anomalies
-
J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian, J. Eisinger, and B. Becker, "A definition and classification of timing anomalies," Int. Workshop on Worst-Case Execution Time Analysis, 2006.
-
(2006)
Int. Workshop on Worst-Case Execution Time Analysis
-
-
Reineke, J.1
Wachter, B.2
Thesing, S.3
Wilhelm, R.4
Polian, I.5
Eisinger, J.6
Becker, B.7
-
36
-
-
77955209042
-
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
-
R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand, "Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009.
-
(2009)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
-
-
Wilhelm, R.1
Grund, D.2
Reineke, J.3
Schlickling, M.4
Pister, M.5
Ferdinand, C.6
-
37
-
-
84861189860
-
Predictability considerations in the design of multi-core embedded systems
-
C. Cullmann, C. Ferdinand, G. Gebhard, D. Grund, C. Maiza, J. Reineke, B. Triquet, and R. Wilhelm, "Predictability considerations in the design of multi-core embedded systems," Embedded Real Time Software and Systems, 2010.
-
(2010)
Embedded Real Time Software and Systems
-
-
Cullmann, C.1
Ferdinand, C.2
Gebhard, G.3
Grund, D.4
Maiza, C.5
Reineke, J.6
Triquet, B.7
Wilhelm, R.8
-
39
-
-
1542330092
-
An abstract interpretation-based timing validation of hard real-time avionics software
-
S. Thesing, R. Heckmann, J. Souyris, F. Randimbivololona, M. Langenbach, R. Wilhelm, and C. Ferdinand, "An abstract interpretation-based timing validation of hard real-time avionics software," 33th Int. Conf. on Dependable Systems and Networks, 2003.
-
(2003)
33th Int. Conf. on Dependable Systems and Networks
-
-
Thesing, S.1
Heckmann, R.2
Souyris, J.3
Randimbivololona, F.4
Langenbach, M.5
Wilhelm, R.6
Ferdinand, C.7
-
42
-
-
84894418339
-
Mulcors-The use of multicore processors in airborne systems
-
X. Jean, M. Gatti, G. Berthon, and M. Fumey, "Mulcors-the use of MULticore proCessORS in airborne systems," European Aviation Safety Agency (EASA), Tech. Rep., 2012.
-
(2012)
European Aviation Safety Agency (EASA), Tech. Rep.
-
-
Jean, X.1
Gatti, M.2
Berthon, G.3
Fumey, M.4
-
46
-
-
84910056590
-
The embedded microprocessor benchmark consortium
-
The Embedded Microprocessor Benchmark Consortium, "EEMBC AutoBench 1. 1 benchmark software," http://www. eembc. org/benchmark/ automotive sl. php.
-
EEMBC AutoBench 1. 1 benchmark software
-
-
|