WCET analysis for multi-core processors with shared L2 instruction caches

Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS

Volumn , Issue , 2008, Pages 80-89

  Yan, Jun ^a   Zhang, Wei ^a  

^a Southern Illinois University Carbondale   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTI CORES; MULTI-CORE PROCESSORS;

ACCESS CONTROL; APPLICATIONS; CACHE MEMORY; COMPUTER NETWORKS; CONCURRENCY CONTROL; EMBEDDED SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 51249094583     PISSN: 15453421     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2008.6     Document Type: Conference Paper

References (24)

1. R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckman, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, P. Stenstrom. The Worstcase execution time problem - overview of methods and survey of tools. In ACM Transactions on Embedded Computing Systems, January 2007.
2. X. Li, Y. Liang, T. Mitra and A. Roychoudhury. Chronos: a timing analyzer for embedded software. http://www.comp.nus.edu.sg/rpembed/chronos, October 2007.
3. C. Ferdinand and R. Wilhelm. Fast and efficient cache behavior prediction for real-time systems. In Real-Time Systems, 17((2/3), 1999.
4. X. Li, A. Roychoudhury, and T. Mitra. Modeling out-of-order processors for software timing analysis. In Proc. of the 25th IEEE International Real-Time Systems Symposium (RTSS'04), 2004.
5. C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proc. of the IEEE Real-Time Systems Symposium, December 1995.
6. F. Stappert, A. Ermedahl and J. Engblom. Efficient longest execution path search for programs with complex flows and pipeline effects. In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2001.
7. Y. S. Li and S. Malik. Performance analysis of embedded software using implicit path enumeration. In Proc. of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Real-Time Systems, 1995.
8. Y. T. S. Li, S. Malik and A. Wolfe. Cache modeling and path analysis for real-time software. In Proc. of the 17th Real-Time Systems Symposium, 1996.
9. G. Ottosson and M. Sjodin. Worst-case execution time analysis for modern hardware architectures. In Proc. of ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems, June 1997.
10. P. Puschner and A. Burns. A review of worstcase execution-time analysis. Journal of Real-Time Systems, 18(2/3): 115-128, May 2000.
11. R. White, F. Muller, C. Healy, D. Whalley, and M. Harmon. Timing analysis for data caches and set-associative caches. In Proc. of the IEEE Real-Time Technology and Applications Symposium, June 1997.
12. H. Ramaprasad and F. Mueller. Bounding worstcase data cache behavior by analytically deriving cache reference patterns. In Proc. of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2005.
13. T. Lundqvist and P. Stenstrom. A method to improve the estimated worst-case performance of data caching. In Proc. of the 6th International Conference on Real-Time Computing Systems and Applications (RTCSA'99), Dec. 1999.
14. J. Staschulat and R. Ernst. Worst case timing analysis of input dependent data cache behavior. In Proc. of the 18th Euromicro Conference on Real-Time Systems (ECRTS06), 2006.
15. C. Berg, J. Engblom and R. Wilhelm. Requirements for and design of a processor with predictable timing. WDSPB, 2004.
16. C. Liu, A. Sivasubramaniam and M. T. Kandemir. Organizing the last line of defense before hitting the memory wall for CMR In Proc. of HPCA, 2004.
17. J. Chang and G. Sohi. Cooperative caching for chip multiprocessors. In Proc. of the 33rd Annual International Symposium on Computer Architecture, 2006.
18. J. Renau et al. SESC simulator. http://sesc.sourceforge.net, Jan. 2005.
19. Homepage of SNU real-time benchmark suite. http://archi.snu.ac.kr/ realtime/benchmark/, Oct 2007.
20. Homepage of CPLEX. http://www.ilog.com/products/cplex/, Oct 2007.
21. J. Calandrino, J. Anderson, and D. Baumberger. A hybrid real-time scheduling approach for large-scale multi-core platforms. In Proc. of the 19th Euromicro Conference on Real-Time Systems, July 2007.
22. J. Calandrino, D. Baumberger, T. Li, S. Hahn, and J. Anderson. Soft real-time scheduling on performance asymmetric multi-core platforms. In Proc. of the 13th IEEE Real-Time and Embedded Technology and Applications Symposium, April 2007.
23. J. H. Anderson, J. M. Calandrino, and U. Devi. Real-time scheduling on multi-core platforms. In Proc. of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium, April 2006.
24. T. Lundqvist and P. Stenstrom. Timing anomalies in dynamically scheduled microprocessors. In Proc. of Real-Time System Symposium, 1999.