Combining abstract interpretation with model checking for timing analysis of multicore software

Proceedings - Real-Time Systems Symposium

Volumn , Issue , 2010, Pages 339-349

  Lv, Mingsong ^a   Yi, Wang ^a,b   Guan, Nan ^a,b   Yu, Ge ^a  

^a NORTHEASTERN UNIVERSITY   (China)

^b UPPSALA UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACT INTERPRETATIONS; ACCESS DELAY; AUTOMATIC GENERATION; CACHE ANALYSIS; CRITICAL RESOURCES; DEDICATED CORES; EMBEDDED REAL TIME SYSTEMS; LOCAL CACHE; LOW ENERGY CONSUMPTION; MEMORY BUS; MULTI CORE; MULTI-CORES; MULTICORE ARCHITECTURES; OFF-CHIP MEMORIES; REAL-TIME PROPERTIES; SHARED BUS; SHARED MEMORIES; TIMED AUTOMATA; TIMING ANALYSIS; UPPAAL MODEL CHECKERS;

ABSTRACTING; AUTOMATA THEORY; AUTOMATIC PROGRAMMING; BUFFER STORAGE; BUSES; EMBEDDED SYSTEMS; ENERGY UTILIZATION; MEMORY ARCHITECTURE; MODEL CHECKING; SOFTWARE ARCHITECTURE;

REAL TIME SYSTEMS;

EID: 79951799430     PISSN: 10528725     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTSS.2010.30     Document Type: Conference Paper

References (29)

1. B. Andersson, A. Easwaran, and J. Lee. Finding an upper bound on the increase in execution time due to contention on the memory bus in COTS-based multicore systems. SIGBED Rev., 7(1):1-4, 2010.
2. D. Andreas, Engelbredt, O. Mads, Chr, T. Martin, H. Rene, Rydhof, and L. Kim, Guldstrand. METAMOC: Modular Execution Time Analysis using Model Checking. in the 10th International Workshop on WCET Analysis, 2010.
3. A. Andrei. Energy Efficient and Predictable Design of Real-Time Embedded Systems. Ph.D. thesis of Linkoping University, Sweden, 2007.
4. A. Andrei, P. Eles, Z. Peng, and J. RosenRosén. Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip. In the 21st International Conference on VLSI Design, 2008.
5. J. Bengtsson and W. Yi. Timed Automata: Semantics, Algorithms and Tools. In Lectures on Concurrency and Petri Nets, pages 87-124. Springer, 2004.
6. R. Bourgade, C. Ballabriga, H. Cass, C. Rochange, and P. Sainrat. Accurate analysis of memory latencies for WCET estimation. 16th International Conference on Real-Time and Network Systems, 2008.
7. S. Chattopadhyay, A. Roychoudhury, and T. Mitra. Modeling shared cache and bus in multi-cores for timing analysis. In 13th International Workshop on Software and Compilers for Embedded Systems, pages 1-10, 2010.
8. C. Ferdinand. Cache Behavior Prediction for Real-Time Systems. Ph.D. thesis of Saarland University, 1997.
9. E. Fersman, L. Mokrushin, P. Pettersson, andW. Yi. Schedulability analysis of fixed-priority systems using timed automata. Theor. Comput. Sci., 2006.
10. D. Grund and J. Reineke. Abstract interpretation of fifo replacement. In the 16th International Symposium on Static Analysis, 2009.
11. N. Guan, M. Stigge, W. Yi, and G. Yu. Cache-aware scheduling and analysis for multicores. In the 7th ACM international conference on Embedded software, 2009.
12. D. Hardy, T. Piquet, and I. Puaut. Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches. In the 30th IEEE Real-Time Systems Symposium, pages 68-77, 2009.
13. D. Hardy and I. Puaut. Wcet analysis of multi-level non-inclusive set-associative instruction caches. In the 29th IEEE Real-Time Systems Symposium, 2008.
14. R. Kirner, A. Kadlec, and P. Puschner. Precise worst-case execution time analysis for processors with timing anomalies. In the 21st Euromicro Conference on Real-Time Systems, 2009.
15. B. Lesage, D. Hardy, and I. Puaut. Wcet analysis of multi-level set-associative data caches. In the 9th International Workshop on Worst-Case Execution Time Analysis, 2009.
16. X. Li, A. Roychoudhury, and T. Mitra. Modeling Out-of-Order Processors for WCET Analysis. Real-Time Syst., 34(3):195-227, 2006.
17. Y. Li, V. Suhendra, Y. Liang, T. Mitra, and A. Roychoudhury. Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores. in the 30th IEEE Real-Time Systems Symposium, pages 57-67, 2009.
18. Y.-T. S. Li and S. Malik. Performance Analysis of Embedded Software using Implicit Path Enumeration. In DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, pages 456-461, 1995.
19. M. Lv, Z. Gu, N. Guan, Q. Deng, and G. Yu. Performance comparison of techniques on static path analysis of wcet. In EUC '08: Proceedings of the 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, pages 104-111, 2008.
20. H. S. Negi, T. Mitra, and A. Roychoudhury. Accurate estimation of cache-related preemption delay. In 1st International conference on Hardware/software codesign and system synthesis, 2003.
21. R. Pellizzoni and M. Caccamo. Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems. IEEE Trans. Comput., 2010.
22. J. Rosén, A. Andrei, P. Eles, and Z. Peng. Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip. In the 28th IEEE International Real-Time Systems Symposium, 2007.
23. A. Schranzhofer, J.-J. Chen, and L. Thiele. Timing Analysis for TDMA Arbitration in Resource Sharing Systems. In the 16th IEEE Real-Time and Embedded Technology and Applications Symposium, 2010.
24. J. Stachulat, S. Schliecker, M. Ivers, and R. Ernst. Analysis of Memory Latencies in Multi-Processor Systems. In 5th Intl. Workshop on WCET Analysis, 2007.
25. V. Suhendra and T. Mitra. Exploring locking & partitioning for predictable shared caches on multi-cores. In the 45th annual Design Automation Conference, 2008.
26. H. Theiling. Control Flow Graphs for Real-Time System Analysis: Reconstruction from Binary Executables and Usage in ILP-Based Paht Analysis. Ph.D. thesis of Saarland University, 2002.
27. S. Williams, A. Waterman, and D. Patterson. Roofline: an Insightful Visual Performance Model for Multicore Architectures. Commun. ACM, 52(4):65-76, 2009.
28. J. Yan and W. Zhang. WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches. In the 14th IEEE Real-Time and Embedded Technology and Applications Symposium, 2008.
29. W. Zhang and J. Yan. Accurately EstimatingWorst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches. In RTCSA, 2009.