메뉴 건너뛰기




Volumn , Issue , 2011, Pages 269-279

A predictable execution model for COTS-based embedded systems

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE COMPONENTS; COTS COMPONENT; CPU CORES; EMBEDDED APPLICATION; EXECUTABLES; EXECUTION MODEL; I/O PERIPHERALS; LLVM COMPILERS; OPERATING POINTS; SAFETY-CRITICAL; SET OF RULES; SHARED RESOURCES; TIMING DELAY;

EID: 79957583292     PISSN: 10801812     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2011.33     Document Type: Conference Paper
Times cited : (222)

References (28)
  • 14
    • 0033732401 scopus 로고    scopus 로고
    • Timing analysis for instruction caches
    • May
    • F. Mueller. Timing analysis for instruction caches. Real Time Systems Journal, 18(2/3):272-282, May 2000.
    • (2000) Real Time Systems Journal , vol.18 , Issue.2-3 , pp. 272-282
    • Mueller, F.1
  • 18
    • 76549093841 scopus 로고    scopus 로고
    • Impact of peripheral-processor interference on wcet analysis of real-time embedded systems
    • Mar
    • R. Pellizzoni and M. Caccamo. Impact of peripheral-processor interference on wcet analysis of real-time embedded systems. IEEE Trans. on Computers, 59(3):400-415, Mar 2010.
    • (2010) IEEE Trans. on Computers , vol.59 , Issue.3 , pp. 400-415
    • Pellizzoni, R.1    Caccamo, M.2
  • 23
  • 27
    • 84874878104 scopus 로고    scopus 로고
    • University of Michigan at Ann Arbor. MiBench Version 1.0, 2001. http://www.eecs.umich.edu/mibench/.
    • (2001) MiBench Version 1.0


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.