Time-analysable non-partitioned shared caches for real-time multicore systems

Proceedings - Design Automation Conference

Volumn , Issue , 2014, Pages

  Slijepcevic, Mladen ^a,b   Kosmidis, Leonidas ^a,b   Abella, Jaume ^a   Quiñones, Eduardo ^a   Cazorla, Francisco J ^a,c  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c ARTIFICIAL INTELLIGENCE RESEARCH INSTITUTE IIIA CSIC   (Spain)

Author keywords

Cache memories; Real time; WCET

Indexed keywords

BUFFER STORAGE; CACHE MEMORY; COMPUTER AIDED DESIGN;

CACHE PARTITIONING; HARDWARE MECHANISM; MULTI-CORE PROCESSOR; MULTI-CORE SYSTEMS; REAL-TIME; SOFTWARE PARTITIONING; WCET; WORST-CASE EXECUTION TIME;

HARDWARE;

EID: 84903186336     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2593069.2593235     Document Type: Conference Paper

References (32)

1. Guidelines and methods for conducting the safety assessment process on civil airborne systems and equipment. ARP4761, 2001.
2. J. Abella, E. Qui~nones, T. Vardanega, and F.J. Cazorla. Measurement-based probabilistic timing analysis and i.i.d property. White Paper. 2013. http://www.proartis-project. eu/publications/MBPTA-white-paper.
3. AUTOSAR. Technical Overview V2.0.1, 2006.
4. G. Bernat, A. Colin, and S.M. Petters. WCET analysis of probabilistic hard real-time systems. In IEEE Real-Time Systems Symposium (RTSS 2002), Austin, Texas (USA), 2002.
5. F.J. Cazorla et al. PROARTIS: Probabilistically analysable real-time systems. ACM TECS, 2013.
6. S. Chattopadhyay, A. Roychoudhury, and T. Mitra. Modeling shared cache and bus in multi-cores for timing analysis. In 13th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2010), St. Goar, Germany, 2010.
7. L. Cucu-Grosjean et al. Measurement-based probabilistic timing analysis for multi-path programs. In 24th Euromicro Conference on Real-Time Systems, (ECRTS 2012), 2012.
8. R. I. Davis, L. Santinelli, S. Altmeyer, C. Maiza, and L. Cucu-Grosjean. Analysis of probabilistic cache related pre-emption delays. In 25th Euromicro Conference on Real-Time Systems, (ECRTS 2013), 2013.
9. W. Feller. An introduction to Probability Theory and Its Applications. John Willer and Sons, 1996.
10. C. Ferdinand and R. Wilhelm. Fast and Efficient Cache Behavior Prediction for Real-Time Systems. Real-Time System, XVII, 1999.
11. J. Hansen, S Hissam, and G. A. Moreno. Statistical-based WCET estimation and validation. In 9th Workshop on Worst-Case Execution Time (WCET) Analysis, 2009.
12. D. Hardy and I. Puaut. WCET analysis of multi-level non-inclusive set-associative instruction caches. In IEEE Real-Time Systems Symposium (RTSS 2008), 2008.
13. J. Jalle, L. Kosmidis, J. Abella, E. Qui~nones, and F.J. Cazorla. Bus designs for time-probabilistic multicore processors. In Design, Automation and Test in Europe (DATE 2014), 2014.
14. H. Kim, A. Kandhalu, and R. Rajkumar. A coordinated approach for practical os-level cache management in multi-core real-time systems. In 25th Euromicro Conference on Real-Time Systems, (ECRTS 2013), Paris, France, 2013.
15. L. Kosmidis, J. Abella, E. Quinones, and F.J. Cazorla. A cache design for probabilistically analysable real-time systems. In Design, Automation and Test in Europe (DATE 2013), 2013.
16. L. Kosmidis, J. Abella, E. Quinones, and F.J. Cazorla. Multi-level unified caches for probabilistically time analysable real-time systems. In IEEE Real-Time Systems Symposium (RTSS), 2013.
17. L. Kosmidis, T. Vardanega, J. Abella, E. Qui~nones, and F.J. Cazorla. Applying measurement-based probabilistic timing analysis to buffer resources. In 13th Workshop on Worst-Case Execution Time (WCET) Analysis, 2013.
18. S. Kotz and S. Nadarajah. Extreme value distributions: theory and applications. World Scientific, 2000.
19. B. Lesage, D. Hardy, and I. Puaut. WCET analysis of multi-level set-associative data caches. 9th Workshop on Worst-Case Execution Time (WCET) Analysis, 2009.
20. J. Liedtke, H. Hartig, and M. Hohmuth. OS-controlled cache predictability for real-time systems. In Real-Time and Embedded Technology and Applications Symp. (RTAS), 1997.
21. G. Marsaglia and A. Zaman. A new class of random number generators. Annals of Applied Probability, 1(3):462-480, 1991.
22. F. Mueller. Predicting instruction cache behavior. Language, Compilers and Tools for Real-Time Systems, 1994.
23. F. Mueller. Compiler support for software-based cache partitioning. In ACM SIGPLAN Conference on Languages, Compilers and Tools for Embedded Systems (LCTES), 1995.
24. M. Paolieri, E. Quinones, F.J. Cazorla, G. Bernat, and M. Valero. Hardware support for WCET analysis of hard real-time multicore systems. In 36th International Symposium on Computer Architecture (ISCA 2009), 2009.
25. M. Paolieri, E. Quinones, F.J. Cazorla, and M. Valero. An Analyzable Memory Controller for Hard Real-Time CMPs . Embedded System Letters (ESL), 2009.
26. J. Poovey. Characterization of the EEMBC Benchmark Suite. North Carolina State University, 2007.
27. J. Reineke, D. Grund, C. Berg, and R. Wilhelm. Timing predictability of cache replacement policies. Real-Time Systems, 37:99-122, November 2007.
28. H. Theiling, C. Ferdinand, and R. Wilhelm. Fast and precise WCET prediction by separated cache andpath analyses. Real-Time Syst., 18(2/3), May 2000.
29. B. Ward, J. Herman, C. Kenna, and J. Anderson. Making shared caches more predictable on multicore platforms. In 25th Euromicro Conf. on Real-Time Systems, (ECRTS), 2013.
30. F. Wartel et al. Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study. In 8th IEEE International Symposium on Industrial Embedded Systems (SIES), Porto, Portugal, 2013.
31. Wilhelm R. et al. The worst-case execution-time problem overview of methods and survey of tools. ACM Transactions on Embedded Computing Systems, 7:1-53, May 2008.
32. W. Zhang and J. Yan. Static timing analysis of shared caches for multicore processors. Journal of Computing Science and Engineering, 6(4), 2012.