NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015

Volumn , Issue , 2015, Pages 283-295

  Farmahini Farahani, Amin ^a   Ahn, Jung Ho ^b   Morrow, Katherine ^a   Kim, Nam Sung ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATION; BANDWIDTH; DATA TRANSFER; ELECTRONICS PACKAGING; ENERGY UTILIZATION; INTEGRATED CIRCUIT INTERCONNECTS; MEMORY ARCHITECTURE; THREE DIMENSIONAL INTEGRATED CIRCUITS;

3-D INTERCONNECTS; IMPROVING PERFORMANCE; OFF-CHIP INTERCONNECTS; PROCESSING ARCHITECTURES; REDUCING ENERGY CONSUMPTION; SYSTEM ENERGY CONSUMPTION; TECHNOLOGY SCALING; THROUGH SILICON VIAS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84934280905     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2015.7056040     Document Type: Conference Paper

References (73)

1. S. W. Keckler et al., "GPUs and the Future of Parallel Computing," IEEE Micro, vol. 31, no. 5, pp. 7-17, Sep. 2011.
2. S. Borkar, "Role of Interconnects in the Future of Computing," J. Light. Technol., vol. 31, no. 24, pp. 3927-3933, Dec. 2013.
3. M. F. Deering et al., "FBRAM: a new form of memory optimized for 3D graphics," in Computer Graphics and Interactive Techniques, 1994, pp. 167-174.
4. J. Draper et al., "The architecture of the DIVA processing-in-memory chip," in Intl. Conf. on Supercomputing, 2002, pp. 14-25.
5. D. G. Elliott et al., "Computational Ram: A memory-SIMD hybrid and its application To DSP," in IEEE Custom Integrated Circuits Conference, 1992, pp. 30. 6. 1-30. 6. 4.
6. D. Keen et al., "FlexRAM: Toward an advanced intelligent memory system," in Intl. Conf. on Computer Design: VLSI in Computers and Processors, 1999, pp. 192-201.
7. K. Mai et al., "Smart Memories: a modular reconfigurable architecture," in Intl. Symp. on Computer Architecture, 2000, pp. 161-171.
8. M. Oskin et al., "Active Pages: A computation model for intelligent memory," in Intl. Symp. on Computer Architecture, 1998, pp. 192-203.
9. D. Patterson et al., "A case for intelligent RAM," IEEE Micro, vol. 17, no. 2, pp. 34-44, 1997.
10. G. H. Loh et al., "A processing in memory taxonomy and a case for studying fixed-function PIM," in Workshop on Near-Data Processing, 2013.
11. D. Patterson et al., "Intelligent RAM (IRAM): the industrial setting, applications, and architectures," in Intl. Conf. on Computer Design, 1997, pp. 2-7.
12. M. Chu et al., "High-level programming model abstractions for processing in memory," in Workshop on Near-Data Processing, 2013.
13. R. G. Dreslinski et al., "Centip3De: A 64-Core, 3D Stacked Near-Threshold System," IEEE Micro, vol. 33, no. 2, pp. 8-16, Mar. 2013.
14. B. Black, "Die stacking is happening (keynote)," in Intl. Symp. on Microarchitecture, 2013.
15. D. H. Kim et al., "3D-MAPS: 3D massively parallel processor with stacked memory," in IEEE Intl. Solid-State Circuits Conference, 2012, pp. 188-190.
16. D. H. Woo et al., "POD: A 3D-Integrated Broad-Purpose Acceleration Layer," IEEE Micro, vol. 28, no. 4, pp. 28-40, Jul. 2008.
17. D. P. Zhang et al., "TOP-PIM: throughput-oriented programmable processing in memory," in Intl. Symp. on High Performance Parallel and Distributed Computing, 2014.
18. Q. Zhu et al., "A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing," in IEEE Intl. 3D Systems Integration Conf., 2013, pp. 1-7.
19. R. Sampson et al., "Sonic Millip3De: A massively parallel 3Dstacked accelerator for 3D ultrasound," in 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013, pp. 318-329.
20. A. Farmahini-Farahani et al., "DRAMA: An Architecture for Accelerated Processing near Memory," IEEE Comput. Archit. Lett., 2014.
21. C. Park et al., "A 512-Mb DDR3 SDRAM Prototype With CIO Minimization and Self-Calibration Techniques," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 831-838, Apr. 2006.
22. Y. H. Son et al., "Reducing memory access latency with asymmetric DRAM bank organizations," in Intl. Symp. on Computer Architecture, 2013, vol. 41, no. 3, pp. 380-391.
23. V. Govindaraju et al., "DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing," IEEE Micro, vol. 32, no. 5, pp. 38-51, Sep. 2012.
24. T. Nowatzki et al., "A general constraint-centric scheduling framework for spatial architectures," in Conf. on Programming Language Design and Implementation, 2013, pp. 495-506.
25. K. Compton and S. Hauck, "Reconfigurable computing: a survey of systems and software," ACM Comput. Surv., vol. 34, no. 2, pp. 171-210, Jun. 2002.
26. Y. Huang et al., "Elastic CGRAs," in Intl. Symp. on Field Programmable Gate Arrays, 2013, pp. 171-180.
27. M. Mishra et al., "Tartan: evaluating spatial computation for whole program execution," in Architectural Support for Programming Languages and Operating Systems, 2006, pp. 163-174.
28. V. Govindaraju et al., "Dynamically specialized datapaths for energy efficient computing," in High Performance Computer Architecture, 2011, pp. 503-514.
29. D. Voitsechov and Y. Etsion, "Single-graph multiple flows: Energy efficient design alternative for GPGPUs," in Intl. Symp. on Computer Architecture, 2014, pp. 205-216.
30. A. Parashar et al., "Triggered instructions: a control paradigm for spatially-programmed architectures," in Intl. Symp. on Computer Architecture, 2013, pp. 142-153.
31. J. L. Tripp et al., "A Survey of Multi-Core Coarse-Grained Reconfigurable Arrays for Embedded Applications," 2008.
32. R. Hartenstein, "Coarse grain reconfigurable architecture," in Asia South Pacific Design Automation Conference, 2001, pp. 564-570.
33. C. Kim et al., "ULP-SRP: Ultra low power Samsung Reconfigurable Processor for biomedical applications," in Intl. Conf. on Field-Programmable Technology, 2012, pp. 329-334.
34. W.-J. Lee et al., "A scalable GPU architecture based on dynamically reconfigurable embedded processor," in High Performance Graphics, Posters, 2011.
35. N. R. Miniskar et al., "Function inlining and loop unrolling for loop acceleration in reconfigurable processors," in Intl. Conf. Compilers, architectures and synthesis for embedded systems, 2012, pp. 101-110.
36. J.-S. Kim et al., "A 1. 2 V 12. 8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4x128 I/Os Using TSV Based Stacking," IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 107-116, Jan. 2012.
37. T. Sekiguchi et al., "1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing," IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 828-837, Apr. 2011.
38. Uksong Kang et al., "8Gb 3D DDR3 DRAM using through-siliconvia technology," in 2009 IEEE International Solid-State Circuits Conference-Digest of Technical Papers, 2009, pp. 130-131,131a.
39. K.-N. Lim et al., "A 1. 2V 23nm 6F2 4Gb DDR3 SDRAM with localbitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture," in IEEE Intl. Solid-State Circuits Conference, 2012, pp. 42-44.
40. K. Sohn et al., "A 1. 2V 30nm 3. 2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme," in IEEE Intl. Solid-State Circuits Conference, 2012, pp. 38-40.
41. M. Shevgoor et al., "Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device," in Intl. Symp. on Microarchitecture, 2013, pp. 198-209.
42. A. R. Lebeck et al., "Power aware page allocation," in Intl. Conf. on Architectural Support for programming Languages and Operating Systems, 2000, vol. 28, no. 5, pp. 105-116.
43. J. Mukundan et al., "Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems," in Intl. Symp. on Computer Architecture, 2013, vol. 41, no. 3, pp. 48-59.
44. A. Basu et al., "Efficient virtual memory for big memory servers," in Intl. Symp. on Computer Architecture, 2013, pp. 237-248.
45. D. Y. Deng et al., "Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric," in Intl. Symp. on Microarchitecture, 2010, pp. 137-148.
46. S. Pugsley et al., "Comparing Different Implementations of Near Data Computing with In-Memory MapReduce Workloads," IEEE Micro, vol. 34, no. 4, pp. 44-52, 2014.
47. J. Ekanayake et al., "MapReduce for Data Intensive Scientific Analyses," in IEEE Intl. Conf. on eScience, 2008, pp. 277-284.
48. S. K. Venkata et al., "SD-VBS: The San Diego Vision Benchmark Suite," in International Symposium on Workload Characterization, 2009, pp. 55-64.
49. J. Stratton et al., "Parboil: A revised benchmark suite for scientific and commercial throughput computing," 2012.
50. "CORAL benchmark codes," 2014. [Online]. Available: https://asc. llnl. gov/CORAL-benchmarks/.
51. S. C. Woo et al., "The SPLASH-2 programs: characterization and methodological considerations," in Intl. Symp. on Computer Architecture, 1995, pp. 24-36.
52. S. Che et al., "Rodinia: A benchmark suite for heterogeneous computing," in Intl. Symp. on Workload Characterization, 2009, pp. 44-54.
53. S. Li et al., "The McPAT Framework for Multicore and Manycore Architectures," ACM Trans. Archit. Code Optim., vol. 10, no. 1, pp. 1-29, Apr. 2013.
54. B. Mei et al., "ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix," in Field Programmable Logic and Application, 2003, pp. 61-70.
55. H. Schmit et al., "PipeRench: A virtualized programmable datapath in 0. 18 micron technology," in Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No. 02CH37285), 2002, pp. 63-66.
56. M. A. Watkins and D. H. Albonesi, "ReMAP: A Reconfigurable Heterogeneous Multicore Architecture," in Intl. Symp. on Microarchitecture, 2010, pp. 497-508.
57. N. Binkert et al., "The gem5 simulator," SIGARCH Comput. Arch. News, vol. 39, no. 2, pp. 1-7, Aug. 2011.
58. K. Chandrasekar et al., "DRAMPower: Open-source DRAM power & energy estimation tool. " [Online]. Available: http://www. drampower. info.
59. R. Hameed et al., "Understanding sources of inefficiency in generalpurpose chips," in Intl. Symp. on Computer Architecture, 2010, pp. 37-47.
60. R. Hou et al., "Efficient data streaming with on-chip accelerators: Opportunities and challenges," in High Performance Computer Architecture, 2011, pp. 312-320.
61. A. Farmahini-Farahani et al., "Energy-Efficient Reconfigurable Cache Architectures for Accelerator-Enabled Embedded Systems," in Intl. Symp. on Performance Analysis of Systems and Software, 2014, pp. 211-220.
62. R. Hartenstein, "A decade of reconfigurable computing: a visionary retrospective," in Design, Automation and Test in Europe, 2001, pp. 642-649.
63. Z. A. Ye et al., "CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit," in Intl. Symp. on Computer Architecture, 2000, pp. 225-235.
64. J. Hauser and J. Wawrzynek, "Garp: a MIPS processor with a reconfigurable coprocessor," in Field-Programmable Custom Computing Machines, 1997, pp. 12-21.
65. T. Callahan et al., "The Garp architecture and C compiler," Computer (Long. Beach. Calif)., vol. 33, no. 4, pp. 62-69, 2000.
66. Q. Guo et al., "A resistive TCAM accelerator for data-intensive computing," in Intl. Symp. on Microarchitecture, 2011, pp. 339-350.
67. Q. Guo et al., "AC-DIMM: associative computing with STTMRAM," in Intl. Symp. on Computer Architecture, 2013, vol. 41, no. 3, pp. 189-200.
68. J. Ahn et al., "Scatter-Add in Data Parallel Architectures," in Intl. Symp. on High-Performance Computer Architecture, 2005, pp. 132-142.
69. R. B. T. Mingliang Wei, Marc Snir, Josep Torrellas, "A near-memory processor for vector, streaming and bit manipulation workloads," in UIUC Tech. Report, 2005.
70. Z. Fang et al., "Active memory controller," J. Supercomput., vol. 62, no. 1, pp. 510-549, Jan. 2012.
71. J. T. Pawlowski, "Hybrid memory cube (HMC)," in Hot Chips 23, 2011.
72. G. H. Loh, "3D-Stacked Memory Architectures for Multi-core Processors," in Intl. Symp. on Computer Architecture, 2008, pp. 453-464.
73. S. O et al., "Row-Buffer Decoupling: A Case for Low-Latency DRAM Microarchitecture," in Intl. Symp. on Computer Architecture, 2014.