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Volumn 17, Issue 2, 1997, Pages 34-43

A case for intelligent ram

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; MICROPROCESSOR CHIPS;

EID: 0031096193     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.592312     Document Type: Article
Times cited : (541)

References (19)
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  • 5
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    • The Transputer
    • D. Aspinall, ed., Cambridge University Press, London
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    • (1978) The Microprocessor and Its Application , pp. 343-357
    • Barron, I.M.1
  • 6
    • 84870766462 scopus 로고
    • Combined DRAM and Logic Chip for Massively Parallel Systems
    • IEEE CS Press
    • P.M. Kogge et al., "Combined DRAM and Logic Chip for Massively Parallel Systems," Proc. 16th Conf. Advanced Research in VLSI, IEEE CS Press, 1995, pp. 4-16.
    • (1995) Proc. 16th Conf. Advanced Research in VLSI , pp. 4-16
    • Kogge, P.M.1
  • 10
    • 0003158656 scopus 로고
    • Hitting the Memory Wall: Implications of the Obvious
    • Mar.
    • W.A. Wulf and S.A. McKee, "Hitting the Memory Wall: Implications of the Obvious," Computer Architecture News, Vol. 23, No. 1, Mar. 1995, pp. 20-24.
    • (1995) Computer Architecture News , vol.23 , Issue.1 , pp. 20-24
    • Wulf, W.A.1    McKee, S.A.2
  • 11
    • 0030685589 scopus 로고    scopus 로고
    • The Energy Efficiency of IRAM Architectures
    • submitted proceedings to be published by IEEE CS Press
    • R. Fromm et al., "The Energy Efficiency of IRAM Architectures," submitted to ISCA 97: The 24th Ann. Int'l Symp. Computer Architecture, proceedings to be published by IEEE CS Press, 1997.
    • (1997) ISCA 97: The 24th Ann. Int'l Symp. Computer Architecture
    • Fromm, R.1
  • 12
    • 0030083522 scopus 로고    scopus 로고
    • A 1MB, 100MHz Integrated L2 Cache Memory and 128b Interface and ECC Protection
    • IEEE
    • G. Giacalone et al., "A 1MB, 100MHz Integrated L2 Cache Memory and 128b Interface and ECC Protection," Proc Int'l Solid-State Circuits Conf., IEEE, 1996, pp. 370-371.
    • (1996) Proc Int'l Solid-State Circuits Conf. , pp. 370-371
    • Giacalone, G.1
  • 13
    • 84995478726 scopus 로고
    • FBRAM: A New Form of Memory Optimized for 3D Graphics
    • Assn. for Computing Machinery, New York
    • M.F. Deering, S.A. Schlapp, and M.G. Lavelle, "FBRAM: A New Form of Memory Optimized for 3D Graphics," Proc. SIGGRAPH 94, Assn. for Computing Machinery, New York, 1994, pp. 167-174.
    • (1994) Proc. SIGGRAPH 94 , pp. 167-174
    • Deering, M.F.1    Schlapp, S.A.2    Lavelle, M.G.3
  • 15
    • 0029666645 scopus 로고    scopus 로고
    • Missing the Memory Wall: The Case for Processor/Memory Integration
    • IEEE CS Press
    • A. Saulsbury, F. Pong, and A. Nowatzk, "Missing the Memory Wall: The Case for Processor/Memory Integration," Int'l Symp. Computer Architecture, IEEE CS Press, 1996, pp. 90-101.
    • (1996) Int'l Symp. Computer Architecture , pp. 90-101
    • Saulsbury, A.1    Pong, F.2    Nowatzk, A.3
  • 18
    • 0030085960 scopus 로고    scopus 로고
    • A 7.68 GIPS 3,84 GB/s 1W Parallel Image Processing RAM Integrating a 16 Mb DRAM and 128 Processors
    • IEEE
    • Y. Aimoto et al., "A 7.68 GIPS 3,84 GB/s 1W Parallel Image Processing RAM Integrating a 16 Mb DRAM and 128 Processors," Dig. Technical Papers, 1996 IEEE Int'l Solid-State Circuits Conf., IEEE, 1996, pp. 372-373, 476.
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    • Aimoto, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.