A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 38-39

  Sohn, Kyomin ^a   Na, Taesik ^a   Song, Indal ^a   Shim, Yong ^a   Bae, Wonil ^a   Kang, Sanghee ^a   Lee, Dongsu ^a   Jung, Hangyun ^a   Jeoung, Hanki ^a   Lee, Ki Won ^a   Park, Junsuk ^a   Lee, Jongeun ^a   Lee, Byunghyun ^a   Jun, Inwoo ^a   Park, Juseop ^a   Park, Junghwan ^a   Choi, Hundai ^a   Kim, Sanghee ^a   Chung, Haeyoung ^a   Choi, Young ^a   Jung, Dae Hee ^a   Choi, Jang Seok ^a   Moon, Byungsick ^a   Choi, Jung Hwan ^a   Kim, Byungchul ^a   Jang, Seong Jin ^a   Choi, Joo Sun ^a   Oh, Kyung Seok ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; CYCLIC REDUNDANCY CHECK; DATA BUS; DATA RATES; HIGH-CAPACITY; HIGH-SPEED; I/O INTERFACES; INITIAL STAGES; LOW SUPPLY VOLTAGES; MULTIMEDIA CONTENTS; RELIABLE TRANSMISSION; SERVER SYSTEM; SUPPLY VOLTAGE REDUCTION;

DRAIN CURRENT; SANITARY SEWERS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84860652243     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176868     Document Type: Conference Paper

References (3)

1. S.-J. Bae, Y.-S. Sohn, K.-I. Park et al., "A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques," ISSCC Dig. Tech. Papers, pp. 278-279, Feb. 2008.
2. T.-Y. Oh, Y.-S. Sohn, S.-J. Bae et al., "A 7Gb/s/pin GDDR5 SDRAM with 2.5ns Bank-to-Bank Active Time and No Bank-Group Restriction," ISSCC Dig. Tech. Papers, pp. 434-435, Feb. 2010.
3. R. Kho, D. Boursin, M. Brox et al., "75nm 7Gb/s/pin 1Gb GDDR5 Graphics Memory Device with Bandwidth-Improvement Techniques," ISSCC Dig. Tech. Papers, pp. 134-135, Feb. 2009.