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Volumn 41, Issue 4, 2006, Pages 831-836

A 512-Mb DDR3 SDRAM prototype with C IO minimization and self-calibration techniques

Author keywords

Calibration; DDR3 SDRAM; Input capacitance; Per bank refresh; SCR type ESD; Signal integrity; Temperature sensor

Indexed keywords

DDR3 SDRAM; INPUT CAPACITANCE; PER-BANK REFRESH; SCR TYPE ESD; SIGNAL INTEGRITY; TEMPERATURE SENSOR;

EID: 33645656262     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870808     Document Type: Conference Paper
Times cited : (39)

References (6)
  • 1
    • 2442670172 scopus 로고    scopus 로고
    • A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application
    • K. Kim et al., "A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 212-523.
    • (2004) IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers , pp. 212-523
    • Kim, K.1
  • 2
    • 2442667590 scopus 로고    scopus 로고
    • A 1.6 Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control
    • S. Lee et al., "A 1.6 Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 210-213.
    • (2004) IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers , pp. 210-213
    • Lee, S.1
  • 4
    • 33645666041 scopus 로고    scopus 로고
    • Samsung Electronics, Sep.
    • DDR2 SDRAM Databook. Samsung Electronics, Sep. 2004, p. 56.
    • (2004) DDR2 SDRAM Databook , pp. 56
  • 5
    • 33645696138 scopus 로고    scopus 로고
    • Samsung Electronics, Mar.
    • Graphic Memory Databook. Samsung Electronics, Mar. 2004, p. 236.
    • (2004) Graphic Memory Databook , pp. 236
  • 6
    • 33645683157 scopus 로고    scopus 로고
    • A 512 Mb, 1.6 Gbps/pin DDR3 SDRAM prototype with Ci o minimization and self-calibration techniques
    • June
    • C. Park et al., "A 512 Mb, 1.6 Gbps/pin DDR3 SDRAM prototype with Ci o minimization and self-calibration techniques," in Symp. VLSI Circuits Dig. Tech. Papers, June 2005, pp. 370-373.
    • (2005) Symp. VLSI Circuits Dig. Tech. Papers , pp. 370-373
    • Park, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.