Efficient data streaming with on-chip accelerators: Opportunities and challenges

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2011, Pages 312-320

  Hou, Rui ^a   Zhang, Lixin ^c   Huang, Michael C ^b,d   Wang, Kun ^a   Franke, Hubertus ^b   Ge, Yi ^a   Chang, Xiaotao ^a  

^a IBM CHINA RESEARCH LAB   (China)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

^d UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATOR ARCHITECTURES; DATA ACCESS; DATA STREAM; DATA STREAMING; DESIGN AND OPTIMIZATION; HARDWARE SCALABILITY; LOGIC UNIT; ON CHIPS; POWER BUDGETS; RESEARCH COMMUNITIES; RESEARCH OPPORTUNITIES; TRANSISTOR DENSITY; WIDE SPECTRUM;

COMPUTER ARCHITECTURE; DATA REDUCTION; DESIGN; MICROPROCESSOR CHIPS; OPTIMIZATION; RESEARCH;

ACCELERATION;

EID: 79955908630     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2011.5749739     Document Type: Conference Paper

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