The architecture of the DIVA processing-in-memory chip

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2002, Pages 14-25

  Draper, Jeff ^a   Chame, Jacqueline ^a   Hall, Mary ^a   Steele, Craig ^a   Barrett, Tim ^a   LaCoss, Jeff ^a   Granacki, John ^a   Shin, Jaewook ^a   Chen, Chun ^a   Kang, Chang Woo ^a   Kim, Ihn ^a   Daglikoca, Gokhan ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Architecture; Memory bandwidth; Processing in memory

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; INTERFACES (COMPUTER); PARALLEL PROCESSING SYSTEMS; VIRTUAL REALITY;

DATA INTENSIVE ARCHITECHTURE (DIVA);

MICROPROCESSOR CHIPS;

EID: 0036374270     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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